VPMOVW2M instruction (AVX10.1)

VPMOVW2M copies the top bit of every word of a vector into a mask register: bit i of the destination is bit 15 of word i, 8, 16 or 32 bits for the XMM, YMM and ZMM forms, and the mask bits above are cleared. It is the word form of VPMOVB2M, whose page explains the uses, a test for negative elements and a selector for a blend; VPMOVM2W goes the other way. It needs AVX512BW. SSE and AVX have no word form of PMOVMSKB, whose byte mask gives two bits per word.

Recorded on Zen 5

Only the sign bit. vpmovw2m k3, xmm24 read 0000h, 0001h, 0001h, FFFFh, 0001h, FFFFh, 7FFFh and 8000h and wrote A8h, bits 3, 5 and 7, clearing bits 63:8 of K3.
Wider forms. The YMM form wrote the 16-bit A105h and the ZMM form the 32-bit 420B5082h, each with the bits above cleared.

In compiled code

With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, Clang compiles _mm512_cmplt_epi16_mask(a, zero) to one VPMOVW2M, while GCC zeroes a register and emits VPCMPW with predicate 1, as for the bytes on VPMOVB2M’s page. _mm512_movepi16_mask is VPMOVW2M in both, followed by KMOVD when the mask goes to a general-purpose register. A blend that takes its selector from the sign of each word, _mm512_mask_blend_epi16(_mm512_movepi16_mask(sel), x, y), is VPMOVW2M and a VPBLENDMW in both. A loop that collects the sign bits of 32 words one by one into a uint32_t became neither: GCC compares into a mask and turns it back into a vector to shift and OR, and Clang moves each sign bit to its place with VPSRLW and VPSLLVD and ORs the results.

AMD’s Zen 5 latency spreadsheet lists VPMOVW2M as one macro-op on pipe FP1 or FP2 with 3, 4 and 6 cycles for XMM, YMM and ZMM, as VPMOVB2M.

Forms

Every encoding of VPMOVW2M that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPMOVW2M k, xmm` VPMOVW2M_MASKmskw_XMMu16_AVX512	`EVEX.128.F3.0F38.W1 29 /r`	AVX10.1 or AVX512BW + AVX512VL
`VPMOVW2M k, ymm` VPMOVW2M_MASKmskw_YMMu16_AVX512	`EVEX.256.F3.0F38.W1 29 /r`	AVX10.1 or AVX512BW + AVX512VL
`VPMOVW2M k, zmm` VPMOVW2M_MASKmskw_ZMMu16_AVX512	`EVEX.512.F3.0F38.W1 29 /r`	AVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k, xmm` `k, ymm` `k, zmm`
Skylake-SP, Ice Lake	1 / 1p0
Sapphire Rapids	3 / 1p0
Zen 4	1 / 1ALU0 ALU1 ALU2 ALU3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

To a mask: each word of the source sets one bit of k1, bit i for word i.

Every word works alike: 8, 16 and 32 words in the xmm, ymm and zmm forms.

Bit i of k1 comes from word i of xmm2. Result bits 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    k1[i] = zmm2.sw[i] < 0
# the other bits of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPMOVW2M k, xmm` `VPMOVW2M k, ymm` `VPMOVW2M k, zmm`
`k`	explicit	write
`xmm, ymm, zmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E7NM

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVW2M, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_movepi16_mask` `__mmask8 _mm_movepi16_mask(__m128i __A)`	`VPMOVW2M k, xmm` EVEX.128 -mavx512vl -mavx512bw
`_mm256_movepi16_mask` `__mmask16 _mm256_movepi16_mask(__m256i __A)`	`VPMOVW2M k, ymm` EVEX.256 -mavx512vl -mavx512bw
`_mm512_movepi16_mask` `__mmask32 _mm512_movepi16_mask(__m512i __A)`	`VPMOVW2M k, zmm` EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512BW_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`AVX512BW_256` AVX10.1	Same as `AVX512BW_128`	Same as `AVX512BW_128`
`AVX512BW_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Same as `AVX512BW_128`

AVX512BW_128