VPMOVWB

VPMOVWB narrows each word to a byte by keeping its low 8 bits: 32 words of a ZMM register become 32 bytes in a YMM register or in memory, 16 from a YMM register and 8 from an XMM one. It is the word to byte form of VPMOVDB and VPMOVDW, whose pages explain the narrowing store; VPMOVSWB and VPMOVUSWB saturate instead, and VPMOVZXBW widens back. It needs AVX512BW.

Recorded on Zen 5#

• Truncation. vpmovwb xmm0, xmm31 turned 0100h, 8000h, 7FFFh and 0055h into 00h, 00h, FFh and 55h, and cleared XMM0 above its 64 bits of result.
• Masked store. vpmovwb qword ptr [mem]{k4}, xmm9, with E5h in the low byte of K4, wrote bytes 0, 2, 5, 6 and 7 and left bytes 1, 3 and 4 of memory as they were.
• Merging. vpmovwb ymm5{k6}, zmm5, narrowing a register into its own low half, kept the old bytes where K6 was clear and zeroed bits 511:256.

In compiled code#

For d[i] = (uint8_t)a[i] over uint16_t arrays, GCC 14 at -O2 with -march=x86-64-v4 narrows two ZMM loads with VPMOVWB into YMM registers and joins them with VINSERTI64X4 for one 64-byte store, while Clang 23 loads 16 words at a time and stores 16 bytes with vpmovwb xmmword ptr [...], ymm0, also in a loop of unknown length that GCC leaves scalar. Both compile _mm512_cvtepi16_epi8 and _mm512_mask_cvtepi16_storeu_epi8 to the register and masked memory forms.

AMD’s Zen 5 latency spreadsheet gives the register forms one macro-op on FP1 or FP2, with 2 cycles from an XMM source and 4 from a YMM or ZMM one, and the store forms two macro-ops, 5 cycles from a YMM or ZMM register, as VPMOVDW.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        ymm1.b[i] = zmm2.w[i]  # the low bits
    elif zeroing:
        ymm1.b[i] = 0
    # else: ymm1.b[i] keeps its value
for i in range(VL // 16, 16):
    ymm1.b[i] = 0
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

for i in range(VL // 16):
    if k1[i]:
        mem.b[i] = zmm2.w[i]  # the low bits
    # else: mem.b[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVWB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD

All 686 AVX10.1 instructions