VPMOVZXBD

VPMOVZXBD is the VEX and EVEX form of SSE4.1’s PMOVZXBD, whose page covers the widening of unsigned bytes to doublewords. The source is a quarter of the result: 4 bytes for an xmm destination (AVX), 8 for ymm (AVX2) and 16 for zmm (AVX512F; the EVEX xmm and ymm forms also need AVX512VL, or AVX10.1), from memory at any alignment. The bytes stay in order across lanes: on Zen 5, vpmovzxbd ymm0, xmm13 widened bytes 4 to 7 of XMM13, 80h, 7Fh, 00h and 0Fh, into the upper 128-bit lane, and cleared bits 511:256 of ZMM0, which PMOVZXBD would keep.

Widening in place#

The EVEX forms add a write mask per doubleword. Source and destination may be the same register, and the source is read whole before anything is written: the recorded vpmovzxbd zmm9{k3}, xmm9 turned bytes 5 to 7 of XMM9, 01h, 01h and FFh, into doublewords 5 to 7, although doubleword 1, written by the same instruction, covers those bytes. Doubleword 2, whose mask bit was clear, kept 807FFF01h, the old bytes 8 to 11.

In compiled code#

In our builds at -O2 over fixed-size uint8_t arrays:

• Copied into uint32_t or converted to float, Clang 23 widens eight bytes at a time straight from memory, with -march=x86-64-v3 and x86-64-v4. GCC 14 never uses VPMOVZXBD there: it widens a full vector to words with VPMOVZXBW and then to doublewords, with VPMOVZXWD for the copy but VPMOVSXWD before VCVTDQ2PS, which gives the same result here, since the widened bytes are below 256.
• As indices, f[i] = t[idx[i]] with a float table, Clang widens eight bytes for each VGATHERDPS with -march=x86-64-v4; with x86-64-v3 it loads the elements one by one, and GCC keeps both loops scalar.

AMD’s latency spreadsheet for Zen 5 gives the xmm and ymm forms a latency of 2 cycles and the zmm form 4, two per cycle each. VPMOVSXBD sign-extends instead.

In the optimization guide

What the optimization guide says about VPMOVZXBD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:                  # 1 without a write mask
        zmm1.d[i] = src2.b[i]  # zero-extended
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E5

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVZXBD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND

All 253 AVX instructions

More AVX2 instructions

• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND

All 138 AVX2 instructions

More AVX10.1 instructions

• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ

All 686 AVX10.1 instructions