x86-64.net

Instruction

VPMOVZXBQ

Zero-extends packed bytes to quadwords.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPMOVZXBQ is the VEX and EVEX form of SSE4.1’s PMOVZXBQ, whose page covers the zero extension of bytes to quadwords. The source is an eighth of the result: 2 bytes for an xmm destination (AVX), 4 for ymm (AVX2) and 8 for zmm (AVX512F; the EVEX xmm and ymm forms also need AVX512VL, or AVX10.1), from memory at any alignment. On Zen 5, vpmovzxbq ymm1, xmm2 turned bytes 80h, 7Fh, 00h and 0Fh into four quadwords, the last two in the upper 128-bit lane, and cleared bits 511:256 of ZMM1. The EVEX forms add a write mask per quadword: in the recorded vpmovzxbq zmm5{k4}, xmm5, quadwords 5 to 7 got bytes 5 to 7 of the source, 01h, 01h and FFh, although quadword 0, written as 10h by the same instruction, covers those bytes, and quadword 1, its mask bit clear, kept 7F807F80807FFF01h, the old bytes 8 to 15.

Narrow data in 64-bit sums

A sum of uint8_t values into a uint64_t total cannot overflow, and in our builds at -O2 with -march=x86-64-v3 or x86-64-v4 Clang 23 compiles it to VPMOVZXBQ straight from memory, four bytes at a time, and VPADDQ. GCC 14 never emits VPMOVZXBQ for it: it loads a full vector and widens in three steps, VPMOVZXBW, VPMOVZXWD and VPMOVZXDQ, with a VEXTRACTI128 for each upper half, or the same on zmm registers for x86-64-v4.

Bytes used as indices into a table of 64-bit values do not need quadword indices: for q[i] = t[idx[i]] with uint8_t indices, Clang with -march=x86-64-v4 widens four bytes to doublewords with VPMOVZXBD for each VPGATHERDQ, since a byte is never large enough for the sign of a doubleword index to matter. GCC keeps that loop scalar.

AMD’s latency spreadsheet for Zen 5 gives the xmm and ymm forms a latency of 2 cycles and the zmm form 4, two per cycle each. VPMOVSXBQ sign-extends instead.

In the optimization guide

What the optimization guide says about VPMOVZXBQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

  • Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Forms

Every encoding of VPMOVZXBQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMOVZXBQ xmm, xmm VPMOVZXBQ_XMMdq_XMMwVEX.128.66.0F38.WIG 32 /rAVX
VPMOVZXBQ xmm, m16 VPMOVZXBQ_XMMdq_MEMwVEX.128.66.0F38.WIG 32 /rAVX
VPMOVZXBQ ymm, xmm VPMOVZXBQ_YMMqq_XMMdVEX.256.66.0F38.WIG 32 /rAVX2
VPMOVZXBQ ymm, m32 VPMOVZXBQ_YMMqq_MEMdVEX.256.66.0F38.WIG 32 /rAVX2
VPMOVZXBQ zmm {k}{z}, xmm VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512EVEX.512.66.0F38.WIG 32 /rAVX10.1 or AVX512F
VPMOVZXBQ zmm {k}{z}, m64 VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512EVEX.512.66.0F38.WIG 32 /rAVX10.1 or AVX512F
VPMOVZXBQ xmm {k}{z}, xmm VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512EVEX.128.66.0F38.WIG 32 /rAVX10.1 or AVX512F + AVX512VL
VPMOVZXBQ xmm {k}{z}, m16 VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512EVEX.128.66.0F38.WIG 32 /rAVX10.1 or AVX512F + AVX512VL
VPMOVZXBQ ymm {k}{z}, xmm VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512EVEX.256.66.0F38.WIG 32 /rAVX10.1 or AVX512F + AVX512VL
VPMOVZXBQ ymm {k}{z}, m32 VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512EVEX.256.66.0F38.WIG 32 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm
xmm {k}{z}, xmm		xmm, m16ymm, xmm
ymm {k}{z}, xmm		ymm, m32
zmm {k}{z}, m64
ymm {k}{z}, m32		zmm {k}{z}, xmmxmm {k}{z}, m16
Sandy Bridge1 / 0.5p157 / 0.5p15
Haswell, Skylake1 / 1p56 / 1p53 / 1p510 / 1p5
Broadwell1 / 1p56 / 1p53 / 1p59 / 1p5
Skylake-SP1 / 1p56 / 1p53 / 1p510 / 1p53 / 1p57 / 1p5
Ice Lake1 / 0.5p157 / 0.5p153 / 1p510 / 1p53 / 1p57 / 0.5p15
Alder Lake1 / 0.5p158 / 0.5p153 / 1p511 / 1p5
Sapphire Rapids1 / 0.5p158 / 0.5p153 / 1p511 / 1p53 / 1p58 / 0.5p15
Lunar Lake1 / 0.5V2 V38 / 0.5V2 V33 / 0.5V2 V310 / 2.33V2 V3
Piledriver2 / 1FPU1 FPXBR7 / 1.5FPU1 FPXBR
Zen1 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 2FPU1 FPU28 / 2FPU1 FPU2
Zen 21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU24 / 0.5FPU1 FPU28 / 0.5FPU1 FPU2
Zen 31 / 0.5FP1 FP28 / 0.5FP1 FP24 / 1.5FP1 FP211 / 1.5FP1 FP2
Zen 42 / 0.5FP1 FP28 / 0.5FP1 FP22 / 0.5FP1 FP211 / 1.5FP1 FP24 / 1FP1 FP28 / 0.5FP1 FP2
Jaguar1 / 0.5FPU0 FPU1 VALU0 VALU16 / 1FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each byte becomes a quadword, zero-extended, in the same order.
VPMOVZXBQ: each element widenedResult quadwords 7 to 0: a7, unchanged (bit 6 of k1 is 0), a5, a4, a3, a2, a1, a0.…01234567xmm2or m64a11111110k1a0a1a2a3a4a5a7zmm1

The grey upper part of each quadword is the extension: zeros. Shown for the zmm form; the xmm and ymm forms work the same on 2 and 4 bytes. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result quadwords 7 to 0: a7, unchanged (bit 6 of k1 is 0), a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:                  # 1 without a write mask
        zmm1.q[i] = src2.b[i]  # zero-extended
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPMOVZXBQ xmm, xmm/m16 VPMOVZXBQ ymm, xmm/m32
xmm, ymmexplicitwrite
xmm/m16/32explicitread
VPMOVZXBQ xmm {k}{z}, xmm/m16 VPMOVZXBQ ymm {k}{z}, xmm/m32 VPMOVZXBQ zmm {k}{z}, xmm/m64
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m16/32/64explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-5
EVEX forms
AVX512-E5

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVZXBQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtepu8_epi64 __m128i _mm_cvtepu8_epi64(__m128i __V)

VPMOVZXBQ xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_cvtepu8_epi64 __m128i _mm_mask_cvtepu8_epi64(__m128i __W, __mmask8 __U, __m128i __A)

VPMOVZXBQ xmm {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_cvtepu8_epi64 __m128i _mm_maskz_cvtepu8_epi64(__mmask8 __U, __m128i __A)

VPMOVZXBQ xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm256_cvtepu8_epi64 __m256i _mm256_cvtepu8_epi64(__m128i __V)

VPMOVZXBQ ymm, xmm VEX.256 -mavx2

_mm256_mask_cvtepu8_epi64 __m256i _mm256_mask_cvtepu8_epi64(__m256i __W, __mmask8 __U, __m128i __A)

VPMOVZXBQ ymm {k}, xmm EVEX.256 -mavx512vl

_mm256_maskz_cvtepu8_epi64 __m256i _mm256_maskz_cvtepu8_epi64(__mmask8 __U, __m128i __A)

VPMOVZXBQ ymm {k}{z}, xmm EVEX.256 -mavx512vl

_mm512_cvtepu8_epi64 __m512i _mm512_cvtepu8_epi64(__m128i __A)

VPMOVZXBQ zmm, xmm EVEX.512 -mavx512f

_mm512_mask_cvtepu8_epi64 __m512i _mm512_mask_cvtepu8_epi64(__m512i __W, __mmask8 __U, __m128i __A)

VPMOVZXBQ zmm {k}, xmm EVEX.512 -mavx512f

_mm512_maskz_cvtepu8_epi64 __m512i _mm512_maskz_cvtepu8_epi64(__mmask8 __U, __m128i __A)

VPMOVZXBQ zmm {k}{z}, xmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-362 (PMOVZX)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.