VPMOVZXBW

VPMOVZXBW widens unsigned bytes to words: each byte of the source becomes a 16-bit element with a zero high byte. Code does this before arithmetic that would overflow a byte, such as summing pixels or counting, and compilers emit it for a loop that adds uint8_t values into uint16_t ones. The result is twice as wide as the source, so the source is half a register: eight bytes for an XMM result, sixteen for YMM, thirty-two for ZMM, from a register or from memory at any alignment.

In order, across the whole register#

Before SSE4.1 the same widening took an unpack with a zeroed register: PUNPCKLBW for the low eight bytes and PUNPCKHBW for the high ones. In a YMM register the two differ. VPUNPCKLBW works within each 128-bit lane and takes bytes 0 to 7 and 16 to 23, while vpmovzxbw ymm, xmm takes bytes 0 to 15 of an XMM register in order and spreads them over both lanes. The way back is not symmetric: VPACKUSWB packs within lanes and needs a VPERMQ to restore the order, while AVX-512’s VPMOVWB narrows in order, by truncation.

What GCC 14 and Clang 23 make of a widening loop at -O2:

• With the x86-64 baseline (SSE2 only), unpacks against a zeroed register.
• With SSE4.1 or AVX2, this instruction. GCC loads a full vector, widens its low half, and moves the high half down with PSRLDQ or VEXTRACTI128 to widen it too; Clang widens straight from memory, sixteen bytes at a time for a YMM result.
• For x86-64-v4, GCC uses the ZMM form, while Clang stays with YMM registers.

Both compilers also replace _mm_unpacklo_epi8(x, zero) with PMOVZXBW once SSE4.1 is enabled, as the two give the same result.

Intel’s optimization guide notes that in the Crestmont microarchitecture the 256-bit form with a memory source takes two micro-ops that depend on each other, while the register form handles its two halves in parallel (Section 4.1.9.3).

The EVEX forms add a mask with one bit per word. PMOVZXBW is the legacy SSE4.1 form; VPMOVSXBW sign-extends, and VPMOVZXBD and VPMOVZXWD widen to other sizes.

In the optimization guide

What the optimization guide says about VPMOVZXBW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:                  # 1 without a write mask
        zmm1.w[i] = src2.b[i]  # zero-extended
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E5

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVZXBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD

All 253 AVX instructions

More AVX2 instructions

• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD

All 138 AVX2 instructions

More AVX10.1 instructions

• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ

All 686 AVX10.1 instructions