x86-64.net

Instruction

VPMOVZXWD

Zero-extends packed words to doublewords.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPMOVZXWD is the VEX and EVEX form of SSE4.1’s PMOVZXWD, whose page covers the widening of unsigned words to doublewords and the SSE2 unpacks it replaces. The source is half the result: 4 words for an xmm destination (AVX), 8 for ymm (AVX2) and 16 for zmm (AVX512F; the EVEX xmm and ymm forms also need AVX512VL, or AVX10.1), from memory at any alignment. On Zen 5, vpmovzxwd ymm0, xmm13 widened words 4 to 7 of XMM13, 0001h, FFFFh, 7FFFh and 8000h, into the upper 128-bit lane as 00000001h, 0000FFFFh, 00007FFFh and 00008000h, and cleared bits 511:256 of ZMM0. The EVEX forms add a write mask per doubleword: vpmovzxwd ymm24{k7}{z}, xmm3 zeroed doublewords 2 to 4, whose mask bits were clear.

Signed products

C multiplies two int16_t values as int, so c[i] = a[i] * b[i] into int32_t needs the full 32-bit product. In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, Clang 23 zero-extends both factors with VPMOVZXWD, although they are signed, and multiplies with VPMADDWD, which multiplies signed words and adds each pair of products. The upper words are zero, so each sum is the product of the low words alone. GCC 14 computes the low and high halves of the products with VPMULLW and VPMULHW for -march=x86-64-v3 and interleaves them with VPUNPCKLWD and VPUNPCKHWD; for x86-64-v4 it sign-extends with VPMOVSXWD and multiplies doublewords with VPMULLD.

For uint16_t factors and a uint32_t product, Clang widens with VPMOVZXWD and uses VPMULLD; GCC does the same on zmm registers for x86-64-v4, and for x86-64-v3 interleaves halves from VPMULLW and VPMULHUW.

AMD’s latency spreadsheet for Zen 5 gives the xmm and ymm forms a latency of 2 cycles and the zmm form 4, two per cycle each.

In the optimization guide

What the optimization guide says about VPMOVZXWD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

  • Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Forms

Every encoding of VPMOVZXWD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMOVZXWD xmm, xmm VPMOVZXWD_XMMdq_XMMqVEX.128.66.0F38.WIG 33 /rAVX
VPMOVZXWD xmm, m64 VPMOVZXWD_XMMdq_MEMqVEX.128.66.0F38.WIG 33 /rAVX
VPMOVZXWD ymm, xmm VPMOVZXWD_YMMqq_XMMdqVEX.256.66.0F38.WIG 33 /rAVX2
VPMOVZXWD ymm, m128 VPMOVZXWD_YMMqq_MEMdqVEX.256.66.0F38.WIG 33 /rAVX2
VPMOVZXWD zmm {k}{z}, ymm VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512EVEX.512.66.0F38.WIG 33 /rAVX10.1 or AVX512F
VPMOVZXWD zmm {k}{z}, m256 VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512EVEX.512.66.0F38.WIG 33 /rAVX10.1 or AVX512F
VPMOVZXWD xmm {k}{z}, xmm VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512EVEX.128.66.0F38.WIG 33 /rAVX10.1 or AVX512F + AVX512VL
VPMOVZXWD xmm {k}{z}, m64 VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512EVEX.128.66.0F38.WIG 33 /rAVX10.1 or AVX512F + AVX512VL
VPMOVZXWD ymm {k}{z}, xmm VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512EVEX.256.66.0F38.WIG 33 /rAVX10.1 or AVX512F + AVX512VL
VPMOVZXWD ymm {k}{z}, m128 VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512EVEX.256.66.0F38.WIG 33 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm
xmm {k}{z}, xmm		xmm, m64ymm, xmm
ymm {k}{z}, xmm		ymm, m128zmm {k}{z}, ymmzmm {k}{z}, m256
ymm {k}{z}, m128		xmm {k}{z}, m64
Sandy Bridge1 / 0.5p157 / 0.5p15
Haswell, Skylake1 / 1p56 / 1p53 / 1p59 / 1p5
Broadwell1 / 1p56 / 1p53 / 1p58 / 1p5
Skylake-SP1 / 1p56 / 1p53 / 1p59 / 1p53 / 1p510 / 1p57 / 1p5
Ice Lake1 / 0.5p157 / 0.5p153 / 1p59 / 1p53 / 1p510 / 1p57 / 0.5p15
Alder Lake1 / 0.5p158 / 0.5p153 / 1p511 / 1p5
Sapphire Rapids1 / 0.5p158 / 0.5p153 / 1p511 / 1p53 / 1p511 / 1p58 / 0.5p15
Lunar Lake1 / 0.5V2 V38 / 0.5V2 V33 / 0.5V2 V310 / 2.33V2 V3
Piledriver2 / 1FPU1 FPXBR7 / 1.5FPU1 FPXBR
Zen1 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 2FPU1 FPU28 / 2FPU1 FPU2
Zen 21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU24 / 0.5FPU1 FPU28 / 0.5FPU1 FPU2
Zen 31 / 0.5FP1 FP28 / 0.5FP1 FP24 / 1.5FP1 FP211 / 1.5FP1 FP2
Zen 42 / 0.5FP1 FP28 / 0.5FP1 FP22 / 0.5FP1 FP211 / 1.5FP1 FP24 / 1FP1 FP211 / 1.5FP1 FP28 / 0.5FP1 FP2
Jaguar1 / 0.5FPU0 FPU1 VALU0 VALU16 / 1FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each word becomes a doubleword, zero-extended, in the same order.
VPMOVZXWD: each element widenedResult doublewords 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.0123456789101112131415ymm2or m256a1111111111111110k1a0a1a2a3a4a5a6a7a8a9a10a11a12a13a15zmm1

The grey upper half of each doubleword is the extension: zeros. Shown for the zmm form; the xmm and ymm forms work the same on 4 and 8 words. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result doublewords 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:                  # 1 without a write mask
        zmm1.d[i] = src2.w[i]  # zero-extended
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPMOVZXWD xmm, xmm/m64 VPMOVZXWD ymm, xmm/m128
xmm, ymmexplicitwrite
xmm/m64/128explicitread
VPMOVZXWD xmm {k}{z}, xmm/m64 VPMOVZXWD ymm {k}{z}, xmm/m128 VPMOVZXWD zmm {k}{z}, ymm/m256
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m64, xmm/m128, ymm/m256explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-5
EVEX forms
AVX512-E5

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVZXWD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtepu16_epi32 __m128i _mm_cvtepu16_epi32(__m128i __V)

VPMOVZXWD xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_cvtepu16_epi32 __m128i _mm_mask_cvtepu16_epi32(__m128i __W, __mmask8 __U, __m128i __A)

VPMOVZXWD xmm {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_cvtepu16_epi32 __m128i _mm_maskz_cvtepu16_epi32(__mmask8 __U, __m128i __A)

VPMOVZXWD xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm256_cvtepu16_epi32 __m256i _mm256_cvtepu16_epi32(__m128i __V)

VPMOVZXWD ymm, xmm VEX.256 -mavx2

_mm256_mask_cvtepu16_epi32 __m256i _mm256_mask_cvtepu16_epi32(__m256i __W, __mmask8 __U, __m128i __A)

VPMOVZXWD ymm {k}, xmm EVEX.256 -mavx512vl

_mm256_maskz_cvtepu16_epi32 __m256i _mm256_maskz_cvtepu16_epi32(__mmask8 __U, __m128i __A)

VPMOVZXWD ymm {k}{z}, xmm EVEX.256 -mavx512vl

_mm512_cvtepu16_epi32 __m512i _mm512_cvtepu16_epi32(__m256i __A)

VPMOVZXWD zmm, ymm EVEX.512 -mavx512f

_mm512_mask_cvtepu16_epi32 __m512i _mm512_mask_cvtepu16_epi32(__m512i __W, __mmask16 __U, __m256i __A)

VPMOVZXWD zmm {k}, ymm EVEX.512 -mavx512f

_mm512_maskz_cvtepu16_epi32 __m512i _mm512_maskz_cvtepu16_epi32(__mmask16 __U, __m256i __A)

VPMOVZXWD zmm {k}{z}, ymm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-362 (PMOVZX)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.