x86-64.net

Instruction

VPMULDQ

Multiplies the signed low doublewords of each quadword into 64-bit products.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPMULDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMULDQ xmm, xmm, m128 VPMULDQ_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.WIG 28 /rAVX
VPMULDQ xmm, xmm, xmm VPMULDQ_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.WIG 28 /rAVX
VPMULDQ ymm, ymm, m256 VPMULDQ_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.WIG 28 /rAVX2
VPMULDQ ymm, ymm, ymm VPMULDQ_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.WIG 28 /rAVX2
VPMULDQ zmm {k}{z}, zmm, zmm VPMULDQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512EVEX.512.66.0F38.W1 28 /rAVX10.1 or AVX512F
VPMULDQ zmm {k}{z}, zmm, m512/m64bcst VPMULDQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512EVEX.512.66.0F38.W1 28 /rAVX10.1 or AVX512F
VPMULDQ xmm {k}{z}, xmm, xmm VPMULDQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512EVEX.128.66.0F38.W1 28 /rAVX10.1 or AVX512F + AVX512VL
VPMULDQ xmm {k}{z}, xmm, m128/m64bcst VPMULDQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512EVEX.128.66.0F38.W1 28 /rAVX10.1 or AVX512F + AVX512VL
VPMULDQ ymm {k}{z}, ymm, ymm VPMULDQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512EVEX.256.66.0F38.W1 28 /rAVX10.1 or AVX512F + AVX512VL
VPMULDQ ymm {k}{z}, ymm, m256/m64bcst VPMULDQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512EVEX.256.66.0F38.W1 28 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMULDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mul_epi32 __m128i _mm_mul_epi32(__m128i __V1, __m128i __V2)

VPMULDQ xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_mul_epi32 __m128i _mm_mask_mul_epi32(__m128i __W, __mmask8 __M, __m128i __X, __m128i __Y)

VPMULDQ xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_mul_epi32 __m128i _mm_maskz_mul_epi32(__mmask8 __M, __m128i __X, __m128i __Y)

VPMULDQ xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm256_mul_epi32 __m256i _mm256_mul_epi32(__m256i __a, __m256i __b)

VPMULDQ ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_mul_epi32 __m256i _mm256_mask_mul_epi32(__m256i __W, __mmask8 __M, __m256i __X, __m256i __Y)

VPMULDQ ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_mul_epi32 __m256i _mm256_maskz_mul_epi32(__mmask8 __M, __m256i __X, __m256i __Y)

VPMULDQ ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm512_mul_epi32 __m512i _mm512_mul_epi32(__m512i __X, __m512i __Y)

VPMULDQ zmm, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_mul_epi32 __m512i _mm512_mask_mul_epi32(__m512i __W, __mmask8 __M, __m512i __X, __m512i __Y)

VPMULDQ zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_mul_epi32 __m512i _mm512_maskz_mul_epi32(__mmask8 __M, __m512i __X, __m512i __Y)

VPMULDQ zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.