x86-64.net

Instruction

VPMULHRSW

Multiplies packed signed words as Q15 fixed-point numbers, rounding each product to a Q15 result.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPMULHRSW multiplies signed words and keeps the rounded high part of each product: a result word is the 32-bit product plus 4000h, shifted right by 15. Read as Q15 fixed-point numbers, with 15 fraction bits for values from -1 up to just below 1, that is the product of two fractions rounded to the nearest Q15 value, halves rounded up. It is the VEX and EVEX form of SSSE3’s PMULHRSW: VEX for xmm with AVX and ymm with AVX2, EVEX with AVX512BW for zmm, write masks and 32 registers. VPMULHW is the plain high half, bits 31 to 16 without rounding, which drops one more bit for Q15 data.

The one overflow

Nothing saturates. Every product fits the result except one: 8000h times 8000h, -1 times -1 in Q15, gives +1, which a word cannot hold, and the result wraps to 8000h, -1 again, with no flag. Zen 5 recorded exactly that, and 7FFFh times 7FFFh gave 7FFEh. Code that may meet two values of -32,768 at once keeps one operand away from it, as with PMADDWD’s single overflow.

Uses

  • Q15 arithmetic: gains, filter taps and mixing in audio and video code, where each multiply would otherwise take a widening multiply, a rounding add, a shift and a pack.
  • Rounding shifts: with the constant 2^(15-k) as the other operand, the result is x divided by 2^k and rounded to nearest, an arithmetic right shift by k from 1 to 15 that rounds instead of flooring.

In compiled code

GCC 14 at -O2 recognizes the operation in a loop over int16_t arrays written as (int16_t)((((int32_t)a[i] * b[i] >> 14) + 1) >> 1) and emits PMULHRSW with -mssse3, or VPMULHRSW with -march=x86-64-v3 or -march=x86-64-v4. It does not recognize the equivalent (a[i] * b[i] + 0x4000) >> 15, and Clang 23 recognizes neither: it widens to doublewords with VPMADDWD, shifts and narrows. With -march=znver5, Clang computes the second form with VPDPWSSD and an accumulator of 4000h, the rounding constant. The intrinsic is _mm512_mulhrs_epi16 and its kin.

AMD’s Zen 5 guide lists VPMULHRSW as one macro-op with a latency of 3 cycles, as for the other word multiplies.

Forms

Every encoding of VPMULHRSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMULHRSW xmm, xmm, m128 VPMULHRSW_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.WIG 0B /rAVX
VPMULHRSW xmm, xmm, xmm VPMULHRSW_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.WIG 0B /rAVX
VPMULHRSW ymm, ymm, m256 VPMULHRSW_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.WIG 0B /rAVX2
VPMULHRSW ymm, ymm, ymm VPMULHRSW_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.WIG 0B /rAVX2
VPMULHRSW xmm {k}{z}, xmm, xmm VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512EVEX.128.66.0F38.WIG 0B /rAVX10.1 or AVX512BW + AVX512VL
VPMULHRSW xmm {k}{z}, xmm, m128 VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512EVEX.128.66.0F38.WIG 0B /rAVX10.1 or AVX512BW + AVX512VL
VPMULHRSW ymm {k}{z}, ymm, ymm VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512EVEX.256.66.0F38.WIG 0B /rAVX10.1 or AVX512BW + AVX512VL
VPMULHRSW ymm {k}{z}, ymm, m256 VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512EVEX.256.66.0F38.WIG 0B /rAVX10.1 or AVX512BW + AVX512VL
VPMULHRSW zmm {k}{z}, zmm, zmm VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512EVEX.512.66.0F38.WIG 0B /rAVX10.1 or AVX512BW
VPMULHRSW zmm {k}{z}, zmm, m512 VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512EVEX.512.66.0F38.WIG 0B /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128no mask		xmm, xmm, xmm
xmm {k}{z}, xmm, xmmno mask
ymm {k}{z}, ymm, ymmno mask		ymm, ymm, m256
ymm {k}{z}, ymm, m256no mask		ymm, ymm, ymmxmm {k}{z}, xmm, xmmwith a mask, zeroing
ymm {k}{z}, ymm, ymmwith a mask, zeroing		xmm {k}{z}, xmm, m128with a mask, zeroingymm {k}{z}, ymm, m256with a mask, zeroingzmm {k}{z}, zmm, zmmno maskzmm {k}{z}, zmm, zmmwith a mask, zeroingzmm {k}{z}, zmm, m512no maskzmm {k}{z}, zmm, m512with a mask, zeroing
Sandy Bridge11 / 1p05 / 1p0
Haswell11 / 1p05 / 1p012 / 1p05 / 1p0
Broadwell10 / 1p05 / 1p011 / 1p05 / 1p0
Skylake11 / 0.5p015 / 0.5p0112 / 0.5p015 / 0.5p01
Skylake-SP, Ice Lake11 / 0.5p015 / 0.5p0112 / 0.5p015 / 0.5p015 / 0.5p0111 / 0.5p0112 / 0.5p015 / 0.5p055 / 0.5p0512 / 0.5p0512 / 0.5p05
Alder Lake13 / 0.5p015 / 0.5p0113 / 0.5p015 / 0.5p01
Sapphire Rapids13 / 0.5p015 / 0.5p0113 / 0.5p015 / 0.5p017 / 0.5p0114 / 0.5p0114 / 0.5p015 / 1p07 / 1p013 / 1p014 / 1p0
Lunar Lake10 / 2V0 V14 / 2V0 V111 / 2.33V0 V14 / 2V0 V1
Piledriver9 / 1.5FPMMA FPU04 / 1FPMMA FPU0
Zen11 / 1FPU04 / 1FPU011 / 2FPU04 / 2FPU0
Zen 211 / 1FPU04 / 1FPU011 / 1FPU04 / 1FPU0
Zen 310 / 0.5FP0 FP33 / 0.5FP0 FP310 / 0.5FP0 FP33 / 0.5FP0 FP3
Zen 410 / 0.5FP0 FP33 / 0.5FP0 FP310 / 0.5FP0 FP33 / 0.5FP0 FP33 / 0.5FP0 FP310 / 0.5FP0 FP310 / 0.5FP0 FP33 / 1FP0 FP33 / 1FP0 FP310 / 1FP0 FP310 / 1FP0 FP3
Jaguar7 / 1FPU0 VIMUL2 / 1FPU0 VIMUL

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.
VPMULHRSW: element by elementResult word i comes from word i of xmm2 and xmm3. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.01234567xmm2a11111110k1r0r1r2r3r4r5r7xmm101234567xmm3or m128b

Every word works alike: 8, 16 and 32 words in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result word i comes from word i of xmm2 and xmm3. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        sa = zmm2.sw[i]
        sb = src3.sw[i]
        zmm1.w[i] = (sa * sb >> 14) + 1 >> 1
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPMULHRSW xmm, xmm, xmm/m128 VPMULHRSW ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPMULHRSW xmm {k}{z}, xmm, xmm/m128 VPMULHRSW ymm {k}{z}, ymm, ymm/m256 VPMULHRSW zmm {k}{z}, zmm, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMULHRSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mulhrs_epi16 __m128i _mm_mulhrs_epi16(__m128i __a, __m128i __b)

VPMULHRSW xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_mulhrs_epi16 __m128i _mm_mask_mulhrs_epi16(__m128i __W, __mmask8 __U, __m128i __X, __m128i __Y)

VPMULHRSW xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_mulhrs_epi16 __m128i _mm_maskz_mulhrs_epi16(__mmask8 __U, __m128i __X, __m128i __Y)

VPMULHRSW xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_mulhrs_epi16 __m256i _mm256_mulhrs_epi16(__m256i __a, __m256i __b)

VPMULHRSW ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_mulhrs_epi16 __m256i _mm256_mask_mulhrs_epi16(__m256i __W, __mmask16 __U, __m256i __X, __m256i __Y)

VPMULHRSW ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_mulhrs_epi16 __m256i _mm256_maskz_mulhrs_epi16(__mmask16 __U, __m256i __X, __m256i __Y)

VPMULHRSW ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_mulhrs_epi16 __m512i _mm512_mulhrs_epi16(__m512i __A, __m512i __B)

VPMULHRSW zmm, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_mulhrs_epi16 __m512i _mm512_mask_mulhrs_epi16(__m512i __W, __mmask32 __U, __m512i __A, __m512i __B)

VPMULHRSW zmm {k}, zmm, zmm EVEX.512 -mavx512bw

_mm512_maskz_mulhrs_epi16 __m512i _mm512_maskz_mulhrs_epi16(__mmask32 __U, __m512i __A, __m512i __B)

VPMULHRSW zmm {k}{z}, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-375 (PMULHRSW)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.