x86-64.net

Instruction

VPMULLD

Multiplies packed doublewords and keeps the low 32 bits of each product.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPMULLD is PMULLD in VEX and EVEX encodings: each doubleword is multiplied by the matching one of the other source, and the low 32 bits of the 64-bit product are kept, the same for signed and unsigned inputs. The PMULLD page covers that and how compilers weigh it against shifts and additions for constants. The newer encodings add what they add to every integer operation:

  • A separate destination and a memory source at any address, where legacy SSE needs 16-byte alignment.
  • Wider registers. AVX2 brings 256 bits, AVX512F 512 bits, and the VEX.128 form clears the register above bit 127.
  • Masks and a broadcast. The EVEX forms (AVX512F, or AVX10.1) take a write mask per doubleword and can multiply every element by one doubleword from memory ({1to16} for zmm).

In compiled code

At -O2 with -march=x86-64-v3, GCC 14 and Clang 23 compile a[i] = b[i] * c[i] over 1,024 ints to VPMULLD on ymm registers with one source in memory. A constant factor that the compilers do not turn into shifts and additions, such as 12345, is broadcast once before the loop: GCC moves it from a general-purpose register with VMOVD and VPBROADCASTD, Clang broadcasts it from a 4-byte constant in memory. With -march=x86-64-v4, GCC 14 uses zmm registers for these loops and Clang 23 stays with ymm.

On Zen 5

AMD’s latency spreadsheet for Zen 5 gives VPMULLD one entry for xmm, ymm and zmm registers alike: one macro-op on pipe 0 or 1, a latency of 3 cycles and two per cycle, against one cycle and four per cycle for VPADDD. A 64-bit low product per element is VPMULLQ, which needs AVX512DQ.

Zen 5’s 10 recorded cases cover every form, among them a merging vpmulld zmm17{k4} and two that multiply by a broadcast doubleword.

Forms

Every encoding of VPMULLD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMULLD xmm, xmm, m128 VPMULLD_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.WIG 40 /rAVX
VPMULLD xmm, xmm, xmm VPMULLD_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.WIG 40 /rAVX
VPMULLD ymm, ymm, m256 VPMULLD_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.WIG 40 /rAVX2
VPMULLD ymm, ymm, ymm VPMULLD_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.WIG 40 /rAVX2
VPMULLD zmm {k}{z}, zmm, zmm VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512EVEX.512.66.0F38.W0 40 /rAVX10.1 or AVX512F
VPMULLD zmm {k}{z}, zmm, m512/m32bcst VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512EVEX.512.66.0F38.W0 40 /rAVX10.1 or AVX512F
VPMULLD xmm {k}{z}, xmm, xmm VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512EVEX.128.66.0F38.W0 40 /rAVX10.1 or AVX512F + AVX512VL
VPMULLD xmm {k}{z}, xmm, m128/m32bcst VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512EVEX.128.66.0F38.W0 40 /rAVX10.1 or AVX512F + AVX512VL
VPMULLD ymm {k}{z}, ymm, ymm VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512EVEX.256.66.0F38.W0 40 /rAVX10.1 or AVX512F + AVX512VL
VPMULLD ymm {k}{z}, ymm, m256/m32bcst VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512EVEX.256.66.0F38.W0 40 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128/m32bcst		xmm, xmm, xmm
xmm {k}{z}, xmm, xmm
ymm {k}{z}, ymm, ymm		ymm, ymm, m256
ymm {k}{z}, ymm, m256/m32bcst		ymm, ymm, ymmzmm {k}{z}, zmm, zmmzmm {k}{z}, zmm, m512/m32bcst
Sandy Bridge11 / 1p05 / 1p0
Haswell16 / 2p010 / 2p017 / 2p010 / 2p0
Broadwell15 / 2p010 / 2p016 / 2p010 / 2p0
Skylake16 / 1p0110 / 1p0117 / 1p0110 / 1p01
Skylake-SP, Ice Lake16 / 1p0110 / 1p0117 / 1p0110 / 1p0110 / 1p0517 / 1p05
Alder Lake18 / 1p0110 / 1p0118 / 1p0110 / 1p01
Sapphire Rapids18 / 1p0110 / 1p0118 / 1p0110 / 1p0110 / 2p018 / 2p0
Lunar Lake18 / 0.5V0 V1 V2 V310 / 0.5V0 V1 V2 V318 / 0.5V0 V1 V2 V310 / 0.5V0 V1 V2 V3
Piledriver10 / 2FPMAL FPMMA FPU0 FPU15 / 2FPMAL FPMMA FPU0 FPU1
Zen11 / 2FPU04 / 2FPU011 / 4FPU04 / 4FPU0
Zen 211 / 2FPU04 / 2FPU011 / 2FPU04 / 2FPU0
Zen 310 / 0.5FP0 FP33 / 0.5FP0 FP310 / 0.5FP0 FP33 / 0.5FP0 FP3
Zen 410 / 0.5FP0 FP33 / 0.5FP0 FP310 / 0.5FP0 FP33 / 0.5FP0 FP33 / 1FP0 FP310 / 1FP0 FP3
Jaguar9 / 2FPU0 FPU1 VALU0 VALU1 VIMUL4 / 2FPU0 FPU1 VALU0 VALU1 VIMUL

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.
VPMULLD: element by elementResult doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: a3×b3, unchanged (bit 2 of k1 is 0), a1×b1, a0×b0.0123xmm2a1110k1a0×b0a1×b1a3×b3xmm10123xmm3or m128b

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one doubleword from memory stands for every element of the last source.

Result doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: a3×b3, unchanged (bit 2 of k1 is 0), a1×b1, a0×b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = zmm2.d[i] * src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPMULLD xmm, xmm, xmm/m128 VPMULLD ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPMULLD xmm {k}{z}, xmm, xmm/m128/m32bcst VPMULLD ymm {k}{z}, ymm, ymm/m256/m32bcst VPMULLD zmm {k}{z}, zmm, zmm/m512/m32bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMULLD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mullo_epi32 __m128i _mm_mullo_epi32(__m128i __V1, __m128i __V2)

VPMULLD xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_mullo_epi32 __m128i _mm_mask_mullo_epi32(__m128i __W, __mmask8 __M, __m128i __A, __m128i __B)

VPMULLD xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_mullo_epi32 __m128i _mm_maskz_mullo_epi32(__mmask8 __M, __m128i __A, __m128i __B)

VPMULLD xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm256_mullo_epi32 __m256i _mm256_mullo_epi32(__m256i __a, __m256i __b)

VPMULLD ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_mullo_epi32 __m256i _mm256_mask_mullo_epi32(__m256i __W, __mmask8 __M, __m256i __A, __m256i __B)

VPMULLD ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_mullo_epi32 __m256i _mm256_maskz_mullo_epi32(__mmask8 __M, __m256i __A, __m256i __B)

VPMULLD ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm512_mullo_epi32 __m512i _mm512_mullo_epi32(__m512i __A, __m512i __B)

VPMULLD zmm, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_mullo_epi32 __m512i _mm512_mask_mullo_epi32(__m512i __W, __mmask16 __M, __m512i __A, __m512i __B)

VPMULLD zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_mullo_epi32 __m512i _mm512_maskz_mullo_epi32(__mmask16 __M, __m512i __A, __m512i __B)

VPMULLD zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-387 (PMULLD/PMULLQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.