VPMULLQ

VPMULLQ multiplies quadwords element by element and keeps the low 64 bits of each 128-bit product. Those bits do not depend on whether the inputs are signed or unsigned, so one instruction serves int64_t and uint64_t alike, and nothing reports a product that did not fit. It is the quadword member of the family of PMULLW and PMULLD, and the last to arrive: it needs AVX512DQ (with AVX512VL for xmm and ymm), so there is no SSE or AVX2 form, and no vector instruction gives the high half of a 64-bit product.

Before AVX-512#

Without it, a 64-bit product is assembled from 32-bit pieces with PMULUDQ: the product of the low halves, plus the two cross products shifted up by 32 bits; the product of the high halves lies wholly above bit 63. For a loop over 1,024 int64_t elements, a[i] = b[i] * c[i], GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 emit three VPMULUDQs per vector, with the shifts and additions around them. With -march=x86-64-v4 the body becomes VPMULLQ: on zmm registers in GCC, and on ymm in Clang, which keeps to 256 bits unless tuned for a processor such as Zen 4 or Zen 5. Intel’s optimization guide uses the same contrast to show AVX-512’s new quadword instructions: a loop that keeps the larger of the sum and the product of two arrays takes 118 instructions with AVX2 and 30 with AVX-512 (Section 17.13.1, Example 17-22).

Multiplying by a constant#

The compilers weigh VPMULLQ against shifts and additions differently. GCC 14 multiplies 64-bit elements by 10 with two shifts and an addition for x86-64-v4, Zen 5 and Sapphire Rapids alike, and uses VPMULLQ for 1234567. Clang 23 multiplies by 10 with VPMULLQ under -march=x86-64-v4 and -march=znver5, but with shifts and additions under -march=sapphirerapids or -march=skylake-avx512.

Speed#

AMD’s Zen 5 guide lists VPMULLQ as one macro-op with a latency of three cycles, the same as VPMULLD. Intel’s guide names VPMULLQ among the instructions that falsely depend on their destination register in the Golden Cove microarchitecture, and recommends zeroing the destination first with a zero idiom such as VPXORD (Section 2.4.1.2).

In the optimization guide

What the optimization guide says about VPMULLQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Ice Lake to Rocket Lake

• Vectors and AVX-512: LLVM’s tuning for these cores counts VPMULLQ as slow: its model makes it three micro-ops with a latency of 15 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = zmm2.q[i] * src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMULLQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ

All 686 AVX10.1 instructions