VPMULLW

VPMULLW multiplies words and keeps the low 16 bits of each product, the same bits for signed and unsigned inputs: the VEX and EVEX form of SSE2’s PMULLW, whose page covers the wrapping and the full products built with VPMULHW’s high halves. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX512BW (with AVX512VL below 512 bits) or AVX10.1 and add a write mask per word, but no broadcast. Every form writes a separate destination, zeroes it above the vector length and reads memory at any alignment. On Zen 5, vpmullw xmm7, xmm11, xmm7 gave 8000h for 8000h times FFFFh, 8001h for 7FFFh times FFFFh and 0001h for 7FFFh times 7FFFh, and vpmullw xmm7{k7}{z}, xmm12, xmmword ptr [mem] wrote products into words 0, 1, 5, 6 and 7, the ones K7 selects, and zeroed the other three.

In compiled code#

In our builds at -O2 over fixed-size arrays, a[i] = b[i] * c[i] over int16_t is one VPMULLW per vector in GCC 14 and Clang 23 with -march=x86-64-v3, on zmm registers in GCC with -march=x86-64-v4. For a factor of 10, GCC shifts and adds while Clang multiplies by a broadcast constant, as without AVX.

• Bytes. There is still no byte multiply. For uint8_t, GCC unpacks each byte vector with itself, multiplies the words and gathers the low bytes, with VPSHUFB and VPBLENDD at -v3, with VPERMT2W and VPSHUFB at -v4. Clang widens nothing: VPMULLW on the byte pairs leaves the even bytes’ products in the low byte of each word, and VPMADDUBSW with the even bytes masked off gives the odd ones, which VPSLLW moves up.
• A condition. For if (c[i] & 1) a[i] = b[i] * a[i] at -v4, both multiply every word and store under a word mask with VMOVDQU16. GCC builds the mask with VPANDQ and VPCMPNEQW and skips a loop step whose mask is empty with KORTESTD; Clang shifts bit 0 of each word to the top with VPSLLW and moves the sign bits into a mask register with VPMOVW2M.

AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike three cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        zmm1.w[i] = zmm2.w[i] * src3.w[i]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMULLW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLW
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW

All 253 AVX instructions

More AVX2 instructions

• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD

All 138 AVX2 instructions

More AVX10.1 instructions

• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD

All 686 AVX10.1 instructions