VPMULTISHIFTQB

VPMULTISHIFTQB extracts unaligned bytes from quadwords: each byte of the result is the 8 bits of a quadword of the second source that start at the bit that the matching byte of the first source names. Byte i takes its bits from quadword i / 8, so the eight control bytes of each quadword can cut eight fields out of it at eight independent offsets, overlapping or not. It came with AVX512_VBMI alongside VPERMB, and the intrinsic is _mm512_multishift_epi64_epi8(control, data).

Offsets that wrap#

Only the low 6 bits of a control byte count, and the 8 bits wrap around the quadword: the byte is the quadword rotated right by the offset, as ROR would, cut to its low 8 bits. In a case recorded on Zen 5 with the quadword 0123456789ABCDEFh, the control 3Eh gave BCh, whose two low bits came from bits 63 and 62 and the other six from bits 5 to 0, and the control C1h gave F7h, the bits from bit 1 up. A field of fewer than 8 bits needs an AND afterwards: the bits above it come along.

The data quadwords are the operand that may be in memory, with broadcast of one quadword to all. The forms belong to exception class E4NF, without fault suppression: every byte of the data operand is read whatever the write mask says, so a mask cannot keep a load from faulting past the end of a buffer.

Unpacking bit fields#

Intel’s optimization manual decompresses an array of 5-bit values this way (Section 17.17.3, Example 17-28): VPERMB copies each group of five input bytes into its own quadword, VPMULTISHIFTQB with the offsets 0, 5, 10, … 35 cuts eight fields out of each, and VPANDQ with 1Fh in every byte clears the bits above the field, 64 values per iteration. The manual reports 26 times the speed of the scalar loop of shifts and masks.

GCC 14 and Clang 23 do not form it from shifts and masks in C; it comes from the intrinsics.

AMD’s Zen 5 guide lists VPMULTISHIFTQB as one macro-op with a latency of 3 cycles on every register width.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):         # byte i, of quadword i // 8
    x = src3.q[i // 8]
    c = zmm2.b[i] & 63           # the bit it starts at
    if k1[i]:                    # 1 without a write mask
        zmm1.b[i] = ror(x, c, 64) & 0xFF
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# src3 is read whatever the mask: a fault in it is not suppressed
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMULTISHIFTQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ

All 686 AVX10.1 instructions