x86-64.net

Instruction

VPMULTISHIFTQB

For each byte of the result, takes 8 bits from the matching quadword of the second source at a bit offset given by a control byte of the first.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPMULTISHIFTQB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMULTISHIFTQB xmm {k}{z}, xmm, xmm VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512EVEX.128.66.0F38.W1 83 /rAVX10.1 or AVX512VBMI + AVX512VL
VPMULTISHIFTQB xmm {k}{z}, xmm, m128/m64bcst VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512EVEX.128.66.0F38.W1 83 /rAVX10.1 or AVX512VBMI + AVX512VL
VPMULTISHIFTQB ymm {k}{z}, ymm, ymm VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512EVEX.256.66.0F38.W1 83 /rAVX10.1 or AVX512VBMI + AVX512VL
VPMULTISHIFTQB ymm {k}{z}, ymm, m256/m64bcst VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512EVEX.256.66.0F38.W1 83 /rAVX10.1 or AVX512VBMI + AVX512VL
VPMULTISHIFTQB zmm {k}{z}, zmm, zmm VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512EVEX.512.66.0F38.W1 83 /rAVX10.1 or AVX512VBMI
VPMULTISHIFTQB zmm {k}{z}, zmm, m512/m64bcst VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512EVEX.512.66.0F38.W1 83 /rAVX10.1 or AVX512VBMI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMULTISHIFTQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_multishift_epi64_epi8 __m128i _mm_multishift_epi64_epi8(__m128i __X, __m128i __Y)

VPMULTISHIFTQB xmm, xmm, xmm EVEX.128 -mavx512vbmi -mavx512vl

_mm_mask_multishift_epi64_epi8 __m128i _mm_mask_multishift_epi64_epi8(__m128i __W, __mmask16 __M, __m128i __X, __m128i __Y)

VPMULTISHIFTQB xmm {k}, xmm, xmm EVEX.128 -mavx512vbmi -mavx512vl

_mm_maskz_multishift_epi64_epi8 __m128i _mm_maskz_multishift_epi64_epi8(__mmask16 __M, __m128i __X, __m128i __Y)

VPMULTISHIFTQB xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vbmi -mavx512vl

_mm256_multishift_epi64_epi8 __m256i _mm256_multishift_epi64_epi8(__m256i __X, __m256i __Y)

VPMULTISHIFTQB ymm, ymm, ymm EVEX.256 -mavx512vbmi -mavx512vl

_mm256_mask_multishift_epi64_epi8 __m256i _mm256_mask_multishift_epi64_epi8(__m256i __W, __mmask32 __M, __m256i __X, __m256i __Y)

VPMULTISHIFTQB ymm {k}, ymm, ymm EVEX.256 -mavx512vbmi -mavx512vl

_mm256_maskz_multishift_epi64_epi8 __m256i _mm256_maskz_multishift_epi64_epi8(__mmask32 __M, __m256i __X, __m256i __Y)

VPMULTISHIFTQB ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vbmi -mavx512vl

_mm512_multishift_epi64_epi8 __m512i _mm512_multishift_epi64_epi8(__m512i __X, __m512i __Y)

VPMULTISHIFTQB zmm, zmm, zmm EVEX.512 -mavx512vbmi

_mm512_mask_multishift_epi64_epi8 __m512i _mm512_mask_multishift_epi64_epi8(__m512i __W, __mmask64 __M, __m512i __X, __m512i __Y)

VPMULTISHIFTQB zmm {k}, zmm, zmm EVEX.512 -mavx512vbmi

_mm512_maskz_multishift_epi64_epi8 __m512i _mm512_maskz_multishift_epi64_epi8(__mmask64 __M, __m512i __X, __m512i __Y)

VPMULTISHIFTQB zmm {k}{z}, zmm, zmm EVEX.512 -mavx512vbmi

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_VBMI_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512VBMI + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[1] AVX512VBMI
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VBMI_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512VBMI + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[1] AVX512VBMI
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VBMI_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512VBMI
CPUID.(EAX=07H,ECX=0):ECX[1] AVX512VBMI

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.