x86-64.net

Instruction

VPMULUDQ

Multiplies the unsigned low doublewords of each quadword into 64-bit products.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPMULUDQ is PMULUDQ in VEX and EVEX encodings: the low doubleword of each quadword times the low doubleword of the matching quadword of the other source, unsigned, into a full 64-bit product. The PMULUDQ page covers its uses, widening products, division by a constant and big-number arithmetic. The high doublewords play no part: on Zen 5, vpmuludq ymm8, ymm15, ymm0 multiplied FFFFFFFFh by FFFFFFFFh into FFFFFFFE00000001h in its top element, although the quadwords held 7FFFFFFFFFFFFFFFh and 00000001FFFFFFFFh.

What the newer encodings add:

  • Width. Four products per ymm register with AVX2, eight per zmm register with AVX512F, and a separate destination.
  • A mask per quadword, each bit choosing one product.
  • A broadcast quadword, of which again only the low half counts. On Zen 5, vpmuludq zmm0{k2}, zmm31, qword bcst [mem] with 0000000080000000h in memory gave 4000000000000000h for an element whose low doubleword was 80000000h, and 3FFFFFFF80000000h for one holding 7FFFFFFFh.

In compiled code

AVX2 has no 64-bit multiply: the VPMULLQ page shows how GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 assemble the low product of uint64_t elements from three VPMULUDQs, and how -march=x86-64-v4 replaces them with VPMULLQ.

For the widening w[i] = (uint64_t)u[i] * v[i], Clang zero-extends each input with VPMOVZXDQ and multiplies with VPMULUDQ at both levels. GCC spreads the inputs with VPERMQ and VPSHUFD for -v3, but with -v4 zero-extends them and uses VPMULLQ, a full 64-bit multiply where a 32-bit one would do. By AMD’s figures that costs nothing on Zen 5: its latency spreadsheet gives VPMULLQ and VPMULUDQ the same entry, one macro-op on pipe 0 or 1, a latency of 3 cycles and two per cycle, against one cycle and four per cycle for VPADDQ.

Zen 5’s 10 recorded cases cover every form, masked and zeroing, two with a broadcast quadword.

Forms

Every encoding of VPMULUDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMULUDQ xmm, xmm, m128 VPMULUDQ_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG F4 /rAVX
VPMULUDQ xmm, xmm, xmm VPMULUDQ_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG F4 /rAVX
VPMULUDQ ymm, ymm, m256 VPMULUDQ_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG F4 /rAVX2
VPMULUDQ ymm, ymm, ymm VPMULUDQ_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG F4 /rAVX2
VPMULUDQ zmm {k}{z}, zmm, zmm VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512EVEX.512.66.0F.W1 F4 /rAVX10.1 or AVX512F
VPMULUDQ zmm {k}{z}, zmm, m512/m64bcst VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512EVEX.512.66.0F.W1 F4 /rAVX10.1 or AVX512F
VPMULUDQ xmm {k}{z}, xmm, xmm VPMULUDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512EVEX.128.66.0F.W1 F4 /rAVX10.1 or AVX512F + AVX512VL
VPMULUDQ xmm {k}{z}, xmm, m128/m64bcst VPMULUDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512EVEX.128.66.0F.W1 F4 /rAVX10.1 or AVX512F + AVX512VL
VPMULUDQ ymm {k}{z}, ymm, ymm VPMULUDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512EVEX.256.66.0F.W1 F4 /rAVX10.1 or AVX512F + AVX512VL
VPMULUDQ ymm {k}{z}, ymm, m256/m64bcst VPMULUDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512EVEX.256.66.0F.W1 F4 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128/m64bcst		xmm, xmm, xmm
xmm {k}{z}, xmm, xmm
ymm {k}{z}, ymm, ymm		ymm, ymm, m256
ymm {k}{z}, ymm, m256/m64bcst		ymm, ymm, ymmzmm {k}{z}, zmm, zmmzmm {k}{z}, zmm, m512/m64bcst
Sandy Bridge11 / 1p05 / 1p0
Haswell11 / 1p05 / 1p012 / 1p05 / 1p0
Broadwell10 / 1p05 / 1p011 / 1p05 / 1p0
Skylake11 / 0.5p015 / 0.5p0112 / 0.5p015 / 0.5p01
Skylake-SP, Ice Lake11 / 0.5p015 / 0.5p0112 / 0.5p015 / 0.5p015 / 0.5p0512 / 0.5p05
Alder Lake13 / 0.5p015 / 0.5p0113 / 0.5p015 / 0.5p01
Sapphire Rapids13 / 0.5p015 / 0.5p0113 / 0.5p015 / 0.5p015 / 1p013 / 1p0
Lunar Lake9 / 2V0 V13 / 1.5V0 V110 / 2.33V0 V13 / 1.5V0 V1
Piledriver9 / 1.5FPMMA FPU04 / 1FPMMA FPU0
Zen11 / 1FPU04 / 1FPU011 / 2FPU04 / 2FPU0
Zen 211 / 1FPU04 / 1FPU011 / 1FPU04 / 1FPU0
Zen 310 / 0.5FP0 FP33 / 0.5FP0 FP310 / 0.5FP0 FP33 / 0.5FP0 FP3
Zen 410 / 0.5FP0 FP33 / 0.5FP0 FP310 / 0.5FP0 FP33 / 0.5FP0 FP33 / 1FP0 FP310 / 1FP0 FP3
Jaguar7 / 1FPU0 VIMUL2 / 1FPU0 VIMUL

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The even doublewords only: doublewords 2 and 0 of the sources make quadwords 1 and 0 of the result, and so on.
VPMULUDQ: the even elementsResult quadword i comes from doubleword 2i of xmm2 and xmm3. Result quadwords 1 to 0: a2, a0.0213xmm2a11k1a0a2xmm10213xmm3or m128b

The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result quadword i comes from doubleword 2i of xmm2 and xmm3. Result quadwords 1 to 0: a2, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm2.d[2 * i]
        b = src3.d[2 * i]
        zmm1.q[i] = a * b
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPMULUDQ xmm, xmm, xmm/m128 VPMULUDQ ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPMULUDQ xmm {k}{z}, xmm, xmm/m128/m64bcst VPMULUDQ ymm {k}{z}, ymm, ymm/m256/m64bcst VPMULUDQ zmm {k}{z}, zmm, zmm/m512/m64bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m64bcst, ymm/m256/m64bcst, zmm/m512/m64bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMULUDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mul_epu32 __m128i _mm_mul_epu32(__m128i __a, __m128i __b)

VPMULUDQ xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_mul_epu32 __m128i _mm_mask_mul_epu32(__m128i __W, __mmask8 __M, __m128i __X, __m128i __Y)

VPMULUDQ xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_mul_epu32 __m128i _mm_maskz_mul_epu32(__mmask8 __M, __m128i __X, __m128i __Y)

VPMULUDQ xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm256_mul_epu32 __m256i _mm256_mul_epu32(__m256i __a, __m256i __b)

VPMULUDQ ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_mul_epu32 __m256i _mm256_mask_mul_epu32(__m256i __W, __mmask8 __M, __m256i __X, __m256i __Y)

VPMULUDQ ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_mul_epu32 __m256i _mm256_maskz_mul_epu32(__mmask8 __M, __m256i __X, __m256i __Y)

VPMULUDQ ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm512_mul_epu32 __m512i _mm512_mul_epu32(__m512i __X, __m512i __Y)

VPMULUDQ zmm, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_mul_epu32 __m512i _mm512_mask_mul_epu32(__m512i __W, __mmask8 __M, __m512i __X, __m512i __Y)

VPMULUDQ zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_mul_epu32 __m512i _mm512_maskz_mul_epu32(__mmask8 __M, __m512i __X, __m512i __Y)

VPMULUDQ zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-395 (PMULUDQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.