x86-64.net

Instruction

VPOPCNTB

Counts the set bits in each byte.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPOPCNTB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPOPCNTB xmm {k}{z}, xmm VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512EVEX.128.66.0F38.W0 54 /rAVX10.1 or AVX512_BITALG + AVX512VL
VPOPCNTB xmm {k}{z}, m128 VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512EVEX.128.66.0F38.W0 54 /rAVX10.1 or AVX512_BITALG + AVX512VL
VPOPCNTB ymm {k}{z}, ymm VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512EVEX.256.66.0F38.W0 54 /rAVX10.1 or AVX512_BITALG + AVX512VL
VPOPCNTB ymm {k}{z}, m256 VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512EVEX.256.66.0F38.W0 54 /rAVX10.1 or AVX512_BITALG + AVX512VL
VPOPCNTB zmm {k}{z}, zmm VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512EVEX.512.66.0F38.W0 54 /rAVX10.1 or AVX512_BITALG
VPOPCNTB zmm {k}{z}, m512 VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512EVEX.512.66.0F38.W0 54 /rAVX10.1 or AVX512_BITALG

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPOPCNTB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_popcnt_epi8 __m128i _mm_popcnt_epi8(__m128i __A)

VPOPCNTB xmm, xmm EVEX.128 -mavx512vl -mavx512bitalg

_mm_mask_popcnt_epi8 __m128i _mm_mask_popcnt_epi8(__m128i __A, __mmask16 __U, __m128i __B)

VPOPCNTB xmm {k}, xmm EVEX.128 -mavx512vl -mavx512bitalg

_mm_maskz_popcnt_epi8 __m128i _mm_maskz_popcnt_epi8(__mmask16 __U, __m128i __B)

VPOPCNTB xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512bitalg

_mm256_popcnt_epi8 __m256i _mm256_popcnt_epi8(__m256i __A)

VPOPCNTB ymm, ymm EVEX.256 -mavx512vl -mavx512bitalg

_mm256_mask_popcnt_epi8 __m256i _mm256_mask_popcnt_epi8(__m256i __A, __mmask32 __U, __m256i __B)

VPOPCNTB ymm {k}, ymm EVEX.256 -mavx512vl -mavx512bitalg

_mm256_maskz_popcnt_epi8 __m256i _mm256_maskz_popcnt_epi8(__mmask32 __U, __m256i __B)

VPOPCNTB ymm {k}{z}, ymm EVEX.256 -mavx512vl -mavx512bitalg

_mm512_popcnt_epi8 __m512i _mm512_popcnt_epi8(__m512i __A)

VPOPCNTB zmm, zmm EVEX.512 -mavx512bitalg

_mm512_mask_popcnt_epi8 __m512i _mm512_mask_popcnt_epi8(__m512i __A, __mmask64 __U, __m512i __B)

VPOPCNTB zmm {k}, zmm EVEX.512 -mavx512bitalg

_mm512_maskz_popcnt_epi8 __m512i _mm512_maskz_popcnt_epi8(__mmask64 __U, __m512i __B)

VPOPCNTB zmm {k}{z}, zmm EVEX.512 -mavx512bitalg

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_BITALG_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_BITALG + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[12] AVX512_BITALG
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_BITALG_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_BITALG + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[12] AVX512_BITALG
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_BITALG_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_BITALG
CPUID.(EAX=07H,ECX=0):ECX[12] AVX512_BITALG

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.