Instruction
VPOPCNTQ
Counts the set bits in each quadword.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPOPCNTQ zmm {k}{z}, zmm
VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 | EVEX.512.66.0F38.W1 55 /r | AVX10.1 or AVX512_VPOPCNTDQ |
VPOPCNTQ zmm {k}{z}, m512/m64bcst
VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 | EVEX.512.66.0F38.W1 55 /r | AVX10.1 or AVX512_VPOPCNTDQ |
VPOPCNTQ xmm {k}{z}, xmm
VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 | EVEX.128.66.0F38.W1 55 /r | AVX10.1 or AVX512_VPOPCNTDQ + AVX512VL |
VPOPCNTQ xmm {k}{z}, m128/m64bcst
VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 | EVEX.128.66.0F38.W1 55 /r | AVX10.1 or AVX512_VPOPCNTDQ + AVX512VL |
VPOPCNTQ ymm {k}{z}, ymm
VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 | EVEX.256.66.0F38.W1 55 /r | AVX10.1 or AVX512_VPOPCNTDQ + AVX512VL |
VPOPCNTQ ymm {k}{z}, m256/m64bcst
VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 | EVEX.256.66.0F38.W1 55 /r | AVX10.1 or AVX512_VPOPCNTDQ + AVX512VL |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPOPCNTQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_popcnt_epi64
__m128i _mm_popcnt_epi64(__m128i __A) |
|
_mm_mask_popcnt_epi64
__m128i _mm_mask_popcnt_epi64(__m128i __W, __mmask8 __U, __m128i __A) |
|
_mm_maskz_popcnt_epi64
__m128i _mm_maskz_popcnt_epi64(__mmask8 __U, __m128i __A) |
|
_mm256_popcnt_epi64
__m256i _mm256_popcnt_epi64(__m256i __A) |
|
_mm256_mask_popcnt_epi64
__m256i _mm256_mask_popcnt_epi64(__m256i __W, __mmask8 __U, __m256i __A) |
|
_mm256_maskz_popcnt_epi64
__m256i _mm256_maskz_popcnt_epi64(__mmask8 __U, __m256i __A) |
|
_mm512_popcnt_epi64
__m512i _mm512_popcnt_epi64(__m512i __A) |
|
_mm512_mask_popcnt_epi64
__m512i _mm512_mask_popcnt_epi64(__m512i __W, __mmask8 __U, __m512i __A) |
|
_mm512_maskz_popcnt_epi64
__m512i _mm512_maskz_popcnt_epi64(__mmask8 __U, __m512i __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_VPOPCNTDQ_512 | AVX10.1 or AVX512_VPOPCNTDQ | Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Mill |
AVX512_VPOPCNTDQ_128 | AVX10.1 or AVX512_VPOPCNTDQ + AVX512VL | Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512_VPOPCNTDQ_256 | AVX10.1 or AVX512_VPOPCNTDQ + AVX512VL | Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VPMOVUSWB
- VPMOVW2M
- VPMOVWB
- VPMOVZXBD
- VPMOVZXBQ
- VPMOVZXBW
- VPMOVZXDQ
- VPMOVZXWD
- VPMOVZXWQ
- VPMULDQ
- VPMULHRSW
- VPMULHUW
- VPMULHW
- VPMULLD
- VPMULLQ
- VPMULLW
- VPMULTISHIFTQB
- VPMULUDQ
- VPOPCNTB
- VPOPCNTD
- VPOPCNTW
- VPORD
- VPORQ
- VPROLD
- VPROLQ
- VPROLVD
- VPROLVQ
- VPRORD
- VPRORQ
- VPRORVD
- VPRORVQ
- VPSADBW
- VPSCATTERDD
- VPSCATTERDQ
- VPSCATTERQD
- VPSCATTERQQ
- VPSHLDD
- VPSHLDQ
- VPSHLDVD
- VPSHLDVQ
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.