Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

VPOPCNTW counts the set bits of each word of a vector and writes each count, 0 to 16, to the word in the same place: 8 words in an XMM register, 16 in a YMM and 32 in a ZMM one, under a write mask. It is the word form of VPOPCNTB, with which it came in AVX512_BITALG, and whose page explains the nibble-table sequence it replaces and the use of the counts; VPOPCNTD and VPOPCNTQ belong to AVX512_VPOPCNTDQ instead. Neither extension is part of x86-64-v4, while -march=znver5 enables both. A word count is POPCNT of a 16-bit value, element by element, without the flags.

Recorded on Zen 5

  • The edges. {evex} vpopcntw xmm17, xmm30 counted 16 for FFFFh, 15 for 7FFFh and 1 for both 0001h and 8000h.
  • Zeroing. In vpopcntw xmm5{k3}{z}, xmmword ptr [...], with mask bits 2 and 4 clear, those words became 0, while the others got 15, 1, 0, 1, 1 and 1 for 7FFFh, 8000h, 0, 0010h, 0008h and 8000h.

In compiled code

At -O2 over uint16_t arrays, a loop storing __builtin_popcount(a[i]) becomes VPOPCNTW straight from memory with -march=znver5, on ZMM registers in GCC 14 and Clang 23. With -march=x86-64-v4, which lacks BITALG, Clang 23 builds the byte counts with VPSHUFB table lookups and adds each word’s two bytes with a shift and VPADDB, and GCC 14 keeps the scalar POPCNT. _mm512_popcnt_epi16 is one VPOPCNTW, and needs BITALG enabled in both compilers.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP0 or FP3 and 2 cycles, two per cycle, as for VPOPCNTB.

Forms

Every encoding of VPOPCNTW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPOPCNTW xmm {k}{z}, xmm VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512EVEX.128.66.0F38.W1 54 /rAVX10.1 or AVX512_BITALG + AVX512VL
VPOPCNTW xmm {k}{z}, m128 VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512EVEX.128.66.0F38.W1 54 /rAVX10.1 or AVX512_BITALG + AVX512VL
VPOPCNTW ymm {k}{z}, ymm VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512EVEX.256.66.0F38.W1 54 /rAVX10.1 or AVX512_BITALG + AVX512VL
VPOPCNTW ymm {k}{z}, m256 VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512EVEX.256.66.0F38.W1 54 /rAVX10.1 or AVX512_BITALG + AVX512VL
VPOPCNTW zmm {k}{z}, zmm VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512EVEX.512.66.0F38.W1 54 /rAVX10.1 or AVX512_BITALG
VPOPCNTW zmm {k}{z}, m512 VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512EVEX.512.66.0F38.W1 54 /rAVX10.1 or AVX512_BITALG

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm {k}{z}, xmmno maskxmm {k}{z}, xmmwith a mask, zeroingxmm {k}{z}, m128no maskxmm {k}{z}, m128with a mask, zeroingymm {k}{z}, ymmno maskymm {k}{z}, ymmwith a mask, zeroingymm {k}{z}, m256no maskymm {k}{z}, m256with a mask, zeroingzmm {k}{z}, zmmno maskzmm {k}{z}, zmmwith a mask, zeroingzmm {k}{z}, m512no maskzmm {k}{z}, m512with a mask, zeroing
Ice Lake1 / 0.5p011 / 0.5p017 / 0.5p017 / 0.5p011 / 0.5p011 / 0.5p018 / 0.5p018 / 0.5p011 / 1p01 / 1p08 / 1p08 / 1p0
Sapphire Rapids3 / 1p55 / 1p510 / 1p513 / 1p53 / 1p55 / 1p511 / 1p513 / 1p53 / 1p55 / 1p511 / 1p513 / 1p5
Zen 42 / 1FP0 FP12 / 1FP0 FP18 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.
VPOPCNTW: element by elementResult word i comes from word i of xmm2. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.01234567xmm2or m128a11111110k1r0r1r2r3r4r5r7xmm1

Every word works alike: 8, 16 and 32 words in the xmm, ymm and zmm forms. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result word i comes from word i of xmm2. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.w[i] = popcount(src2.w[i])
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPOPCNTW xmm {k}{z}, xmm/m128 VPOPCNTW ymm {k}{z}, ymm/m256 VPOPCNTW zmm {k}{z}, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms
write masking
Memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPOPCNTW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_popcnt_epi16 __m128i _mm_popcnt_epi16(__m128i __A)

VPOPCNTW xmm, xmm EVEX.128 -mavx512vl -mavx512bitalg

_mm_mask_popcnt_epi16 __m128i _mm_mask_popcnt_epi16(__m128i __A, __mmask8 __U, __m128i __B)

VPOPCNTW xmm {k}, xmm EVEX.128 -mavx512vl -mavx512bitalg

_mm_maskz_popcnt_epi16 __m128i _mm_maskz_popcnt_epi16(__mmask8 __U, __m128i __B)

VPOPCNTW xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512bitalg

_mm256_popcnt_epi16 __m256i _mm256_popcnt_epi16(__m256i __A)

VPOPCNTW ymm, ymm EVEX.256 -mavx512vl -mavx512bitalg

_mm256_mask_popcnt_epi16 __m256i _mm256_mask_popcnt_epi16(__m256i __A, __mmask16 __U, __m256i __B)

VPOPCNTW ymm {k}, ymm EVEX.256 -mavx512vl -mavx512bitalg

_mm256_maskz_popcnt_epi16 __m256i _mm256_maskz_popcnt_epi16(__mmask16 __U, __m256i __B)

VPOPCNTW ymm {k}{z}, ymm EVEX.256 -mavx512vl -mavx512bitalg

_mm512_popcnt_epi16 __m512i _mm512_popcnt_epi16(__m512i __A)

VPOPCNTW zmm, zmm EVEX.512 -mavx512bitalg

_mm512_mask_popcnt_epi16 __m512i _mm512_mask_popcnt_epi16(__m512i __A, __mmask32 __U, __m512i __B)

VPOPCNTW zmm {k}, zmm EVEX.512 -mavx512bitalg

_mm512_maskz_popcnt_epi16 __m512i _mm512_maskz_popcnt_epi16(__mmask32 __U, __m512i __B)

VPOPCNTW zmm {k}{z}, zmm EVEX.512 -mavx512bitalg

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512_BITALG_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_BITALG + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[12] AVX512_BITALG
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512_BITALG_256
Same as AVX512_BITALG_128Same as AVX512_BITALG_128
AVX512_BITALG_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_BITALG
CPUID.(EAX=07H,ECX=0):ECX[12] AVX512_BITALG

Same as AVX512_BITALG_128

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-606 (VPOPCNT)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.