Instruction
VPOPCNTW
Counts the set bits in each word.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
VPOPCNTW counts the set bits of each word of a vector and writes each
count, 0 to 16, to the word in the same place: 8 words in an XMM
register, 16 in a YMM and 32 in a ZMM one, under a write mask. It is
the word form of VPOPCNTB, with which it came in
AVX512_BITALG, and whose page explains the nibble-table sequence it
replaces and the use of the counts; VPOPCNTD and
VPOPCNTQ belong to AVX512_VPOPCNTDQ instead.
Neither extension is part of x86-64-v4, while -march=znver5
enables both. A word count is POPCNT of a 16-bit
value, element by element, without the flags.
Recorded on Zen 5
- The edges.
{evex} vpopcntw xmm17, xmm30counted 16 for FFFFh, 15 for 7FFFh and 1 for both 0001h and 8000h. - Zeroing. In
vpopcntw xmm5{k3}{z}, xmmword ptr [...], with mask bits 2 and 4 clear, those words became 0, while the others got 15, 1, 0, 1, 1 and 1 for 7FFFh, 8000h, 0, 0010h, 0008h and 8000h.
In compiled code
At -O2 over uint16_t arrays, a loop storing
__builtin_popcount(a[i]) becomes VPOPCNTW straight from memory with
-march=znver5, on ZMM registers in GCC 14 and Clang 23. With
-march=x86-64-v4, which lacks BITALG, Clang 23 builds the byte counts
with VPSHUFB table lookups and adds each word’s two
bytes with a shift and VPADDB, and GCC 14 keeps the
scalar POPCNT. _mm512_popcnt_epi16 is one VPOPCNTW, and needs BITALG
enabled in both compilers.
AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP0 or FP3 and 2 cycles, two per cycle, as for VPOPCNTB.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPOPCNTW xmm {k}{z}, xmm
VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 | EVEX.128.66.0F38.W1 54 /r | AVX10.1 or AVX512_BITALG + AVX512VL |
VPOPCNTW xmm {k}{z}, m128
VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 | EVEX.128.66.0F38.W1 54 /r | AVX10.1 or AVX512_BITALG + AVX512VL |
VPOPCNTW ymm {k}{z}, ymm
VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 | EVEX.256.66.0F38.W1 54 /r | AVX10.1 or AVX512_BITALG + AVX512VL |
VPOPCNTW ymm {k}{z}, m256
VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 | EVEX.256.66.0F38.W1 54 /r | AVX10.1 or AVX512_BITALG + AVX512VL |
VPOPCNTW zmm {k}{z}, zmm
VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 | EVEX.512.66.0F38.W1 54 /r | AVX10.1 or AVX512_BITALG |
VPOPCNTW zmm {k}{z}, m512
VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 | EVEX.512.66.0F38.W1 54 /r | AVX10.1 or AVX512_BITALG |
Latency and throughput
| Model | xmm {k}{z}, xmmno mask | xmm {k}{z}, xmmwith a mask, zeroing | xmm {k}{z}, m128no mask | xmm {k}{z}, m128with a mask, zeroing | ymm {k}{z}, ymmno mask | ymm {k}{z}, ymmwith a mask, zeroing | ymm {k}{z}, m256no mask | ymm {k}{z}, m256with a mask, zeroing | zmm {k}{z}, zmmno mask | zmm {k}{z}, zmmwith a mask, zeroing | zmm {k}{z}, m512no mask | zmm {k}{z}, m512with a mask, zeroing |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Ice Lake | 1 / 0.5p01 | 1 / 0.5p01 | 7 / 0.5p01 | 7 / 0.5p01 | 1 / 0.5p01 | 1 / 0.5p01 | 8 / 0.5p01 | 8 / 0.5p01 | 1 / 1p0 | 1 / 1p0 | 8 / 1p0 | 8 / 1p0 |
| Sapphire Rapids | 3 / 1p5 | 5 / 1p5 | 10 / 1p5 | 13 / 1p5 | 3 / 1p5 | 5 / 1p5 | 11 / 1p5 | 13 / 1p5 | 3 / 1p5 | 5 / 1p5 | 11 / 1p5 | 13 / 1p5 |
| Zen 4 | 2 / 1FP0 FP1 | 2 / 1FP0 FP1 | 8 / 0.5FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.5FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Every word works alike: 8, 16 and 32 words in the xmm, ymm and zmm forms. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.
Result word i comes from word i of xmm2. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 16):
if k1[i]:
zmm1.w[i] = popcount(src2.w[i])
elif zeroing:
zmm1.w[i] = 0
# else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 6 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VPOPCNTW xmm {k}{z}, xmm/m128 VPOPCNTW ymm {k}{z}, ymm/m256 VPOPCNTW zmm {k}{z}, zmm/m512 | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm/m128, ymm/m256, zmm/m512 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking
- Memory forms
- memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPOPCNTW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_popcnt_epi16
__m128i _mm_popcnt_epi16(__m128i __A) |
|
_mm_mask_popcnt_epi16
__m128i _mm_mask_popcnt_epi16(__m128i __A, __mmask8 __U, __m128i __B) |
|
_mm_maskz_popcnt_epi16
__m128i _mm_maskz_popcnt_epi16(__mmask8 __U, __m128i __B) |
|
_mm256_popcnt_epi16
__m256i _mm256_popcnt_epi16(__m256i __A) |
|
_mm256_mask_popcnt_epi16
__m256i _mm256_mask_popcnt_epi16(__m256i __A, __mmask16 __U, __m256i __B) |
|
_mm256_maskz_popcnt_epi16
__m256i _mm256_maskz_popcnt_epi16(__mmask16 __U, __m256i __B) |
|
_mm512_popcnt_epi16
__m512i _mm512_popcnt_epi16(__m512i __A) |
|
_mm512_mask_popcnt_epi16
__m512i _mm512_mask_popcnt_epi16(__m512i __A, __mmask32 __U, __m512i __B) |
|
_mm512_maskz_popcnt_epi16
__m512i _mm512_maskz_popcnt_epi16(__mmask32 __U, __m512i __B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX512_BITALG_128 | AVX10.1 or AVX512_BITALG + AVX512VL | Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6 |
AVX512_BITALG_256 | Same as AVX512_BITALG_128 | Same as AVX512_BITALG_128 |
AVX512_BITALG_512 | AVX10.1 or AVX512_BITALG | Same as AVX512_BITALG_128 |
More AVX10.1 instructions
- VPMOVW2M
- VPMOVWB
- VPMOVZXBD
- VPMOVZXBQ
- VPMOVZXBW
- VPMOVZXDQ
- VPMOVZXWD
- VPMOVZXWQ
- VPMULDQ
- VPMULHRSW
- VPMULHUW
- VPMULHW
- VPMULLD
- VPMULLQ
- VPMULLW
- VPMULTISHIFTQB
- VPMULUDQ
- VPOPCNTB
- VPOPCNTD
- VPOPCNTQ
- VPORD
- VPORQ
- VPROLD
- VPROLQ
- VPROLVD
- VPROLVQ
- VPRORD
- VPRORQ
- VPRORVD
- VPRORVQ
- VPSADBW
- VPSCATTERDD
- VPSCATTERDQ
- VPSCATTERQD
- VPSCATTERQQ
- VPSHLDD
- VPSHLDQ
- VPSHLDVD
- VPSHLDVQ
- VPSHLDVW
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-606 (VPOPCNT)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.