VPOR instruction (AVX, AVX2)

VPOR computes the bitwise OR of two 128- or 256-bit values into a third register: the VEX form of POR, with a memory operand at any address and, for the 128-bit form, the bits from 128 up cleared. On Zen 5, vpor xmm12, xmm6, xmm6 copied the low 16 bytes of XMM6 and left the other 48 bytes of ZMM12 zero. Like VPAND and VPXOR, it ignores element boundaries, and AVX-512 has no EVEX VPOR: VPORD and VPORQ do the same with a write mask of doublewords or quadwords.

In compiled code

GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 use VPOR to merge bits from several places:

Combining fields. c[i] = a[i] | (b[i] << 8), two byte arrays into one of uint16_t, becomes VPMOVZXBW of each, VPSLLW by 8 and VPOR.
Testing a whole array. Whether any element of an unsigned array is nonzero is an OR of everything into a register, then one test at the end: Clang ORs four accumulators together and applies VPTEST; GCC folds the halves with VPOR and shifts and tests the last doubleword in a general-purpose register.

As with AND, Clang picks VORPS where the result is only stored, for a[i] = b[i] | c[i] | d[i], and VPOR where integer operations follow; GCC uses VPOR for all integer data.

AVX-512

With -march=x86-64-v4, OR is one of the many functions of VPTERNLOGD, which takes three inputs: GCC and Clang compile the three-way OR above to a single VPTERNLOGD with immediate FEh, and Clang uses it in the test loop too. Where only two inputs meet, GCC uses VPORD on zmm registers and Clang keeps its VEX choices.

AMD’s latency spreadsheet for Zen 5 gives VPOR one cycle and four per cycle. Zen 5’s 4 recorded cases cover the register and memory forms at both widths.

Forms

Every encoding of VPOR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPOR xmm, xmm, m128` VPOR_XMMdq_XMMdq_MEMdq	`VEX.128.66.0F.WIG EB /r`	AVX
`VPOR xmm, xmm, xmm` VPOR_XMMdq_XMMdq_XMMdq	`VEX.128.66.0F.WIG EB /r`	AVX
`VPOR ymm, ymm, m256` VPOR_YMMqq_YMMqq_MEMqq	`VEX.256.66.0F.WIG EB /r`	AVX2
`VPOR ymm, ymm, ymm` VPOR_YMMqq_YMMqq_YMMqq	`VEX.256.66.0F.WIG EB /r`	AVX2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Every quadword works alike: 2 and 4 quadwords in the xmm and ymm forms.

Result quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: a1|b1, a0|b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    ymm1.q[i] = ymm2.q[i] | src3.q[i]
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPOR xmm, xmm, xmm/m128` `VPOR ymm, ymm, ymm/m256`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPOR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_or_epi32` `__m128i _mm_or_epi32(__m128i __a, __m128i __b)`	`VPOR xmm, xmm, xmm` VEX.128 -mavx512vl
`_mm_or_epi64` `__m128i _mm_or_epi64(__m128i __a, __m128i __b)`	`VPOR xmm, xmm, xmm` VEX.128 -mavx512vl
`_mm_or_pd` `__m128d _mm_or_pd(__m128d __a, __m128d __b)`	`VPOR xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm_or_si128` `__m128i _mm_or_si128(__m128i __a, __m128i __b)`	`VPOR xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm256_or_epi32` `__m256i _mm256_or_epi32(__m256i __a, __m256i __b)`	`VPOR ymm, ymm, ymm` VEX.256 -mavx512vl
`_mm256_or_epi64` `__m256i _mm256_or_epi64(__m256i __a, __m256i __b)`	`VPOR ymm, ymm, ymm` VEX.256 -mavx512vl
`_mm256_or_si256` `__m256i _mm256_or_si256(__m256i __a, __m256i __b)`	`VPOR ymm, ymm, ymm` VEX.256 -mavx2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

In compiled code#

AVX-512#