Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

VPORD is the EVEX form of VPOR with a write mask that selects doublewords: the bitwise OR of two 128-, 256- or 512-bit values, whose memory operand may be one doubleword repeated, {1to16} at 512 bits. VPORQ is the same with quadwords; unmasked the two give the same bits, and VPANDD shows what the EVEX forms add.

Recorded on Zen 5

  • vpord zmm14{k7}, zmm8, dword bcst [mem] with 1 in memory set bit 0 of the 10 doublewords of ZMM8 that F2E3h selects, so 80000000h became 80000001h and 10h became 11h, and left the other six of ZMM14 alone.
  • vpord ymm24{k6}{z}, ymm3, ymm3 copied the three doublewords that A4h selects, an OR of a value with itself, and zeroed the rest.

In compiled code

GCC 14 at -O2 with -march=x86-64-v4 uses VPORD for int data: d[i] = b[i] | c[i] and d[i] |= 0x80000000 over int arrays, the constant broadcast from a general register by VPBROADCASTD before the loop, and _mm512_or_epi32, _mm512_or_si512 and their masked forms. A broadcast is folded in: _mm512_or_epi32(a, _mm512_set1_epi32(*p)) is vpord zmm0, zmm0, dword ptr [rdi]{1to16}. Clang 23 with -march=x86-64-v4 uses VORPS for all of these, masked ones included; with -mavx512f it uses VPORD for the loops and the masked intrinsics and VPORQ for the unmasked ones.

Neither compiler puts the mask of a condition on the OR. For if (b[i] > 0) d[i] |= c[i];, GCC ORs all sixteen elements with VPORD and stores the result with a masked VMOVDQA32 under the mask of a VPCMPD, skipping the store when no element is selected; Clang does the same on YMM registers with the VEX VPOR.

AMD’s Zen 5 latency spreadsheet gives the EVEX VPORD one cycle and four per cycle on any of the four vector pipes. Zen 5’s 6 recorded cases cover the register and memory forms, broadcast included, at all three widths.

Forms

Every encoding of VPORD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPORD zmm {k}{z}, zmm, zmm VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512EVEX.512.66.0F.W0 EB /rAVX10.1 or AVX512F
VPORD zmm {k}{z}, zmm, m512/m32bcst VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512EVEX.512.66.0F.W0 EB /rAVX10.1 or AVX512F
VPORD xmm {k}{z}, xmm, xmm VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512EVEX.128.66.0F.W0 EB /rAVX10.1 or AVX512F + AVX512VL
VPORD xmm {k}{z}, xmm, m128/m32bcst VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512EVEX.128.66.0F.W0 EB /rAVX10.1 or AVX512F + AVX512VL
VPORD ymm {k}{z}, ymm, ymm VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512EVEX.256.66.0F.W0 EB /rAVX10.1 or AVX512F + AVX512VL
VPORD ymm {k}{z}, ymm, m256/m32bcst VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512EVEX.256.66.0F.W0 EB /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelzmm {k}{z}, zmm, zmmzmm {k}{z}, zmm, m512/m32bcstxmm {k}{z}, xmm, xmm
ymm {k}{z}, ymm, ymm
xmm {k}{z}, xmm, m128/m32bcstymm {k}{z}, ymm, m256/m32bcst
Skylake-SP, Ice Lake1 / 0.5p058 / 0.5p051 / 0.33p0157 / 0.5p0158 / 0.5p015
Sapphire Rapids1 / 0.5p059 / 0.5p051 / 0.33p0158 / 0.33p0159 / 0.33p015
Zen 41 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.
VPORD: element by elementResult doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: a3|b3, unchanged (bit 2 of k1 is 0), a1|b1, a0|b0.0123xmm2a1110k1a0|b0a1|b1a3|b3xmm10123xmm3or m128b

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one doubleword from memory stands for every element of the last source.

Result doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: a3|b3, unchanged (bit 2 of k1 is 0), a1|b1, a0|b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = zmm2.d[i] | src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPORD xmm {k}{z}, xmm, xmm/m128/m32bcst VPORD ymm {k}{z}, ymm, ymm/m256/m32bcst VPORD zmm {k}{z}, zmm, zmm/m512/m32bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms
write masking
Memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPORD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mask_or_epi32 __m128i _mm_mask_or_epi32(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPORD xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_mask_or_ps __m128 _mm_mask_or_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)

VPORD xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512dq

_mm_maskz_or_epi32 __m128i _mm_maskz_or_epi32(__mmask8 __U, __m128i __A, __m128i __B)

VPORD xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_or_ps __m128 _mm_maskz_or_ps(__mmask8 __U, __m128 __A, __m128 __B)

VPORD xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512dq

_mm256_mask_or_epi32 __m256i _mm256_mask_or_epi32(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B)

VPORD ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_mask_or_ps __m256 _mm256_mask_or_ps(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B)

VPORD ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512dq

_mm256_maskz_or_epi32 __m256i _mm256_maskz_or_epi32(__mmask8 __U, __m256i __A, __m256i __B)

VPORD ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_or_ps __m256 _mm256_maskz_or_ps(__mmask8 __U, __m256 __A, __m256 __B)

VPORD ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512dq

_mm512_or_epi32 __m512i _mm512_or_epi32(__m512i __a, __m512i __b)

VPORD zmm, zmm, zmm EVEX.512 -mavx512fClang emits the equivalent VPORQ

_mm512_or_ps __m512 _mm512_or_ps(__m512 __A, __m512 __B)

VPORD zmm, zmm, zmm EVEX.512 -mavx512dq

_mm512_mask_or_epi32 __m512i _mm512_mask_or_epi32(__m512i __src, __mmask16 __k, __m512i __a, __m512i __b)

VPORD zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_or_ps __m512 _mm512_mask_or_ps(__m512 __W, __mmask16 __U, __m512 __A, __m512 __B)

VPORD zmm {k}, zmm, zmm EVEX.512 -mavx512dq

_mm512_maskz_or_epi32 __m512i _mm512_maskz_or_epi32(__mmask16 __k, __m512i __a, __m512i __b)

VPORD zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_or_ps __m512 _mm512_maskz_or_ps(__mmask16 __U, __m512 __A, __m512 __B)

VPORD zmm {k}{z}, zmm, zmm EVEX.512 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-411 (POR)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.