VPORQ

VPORQ is the EVEX form of VPOR with a write mask that selects quadwords: the bitwise OR of two 128-, 256- or 512-bit values, whose memory operand may be one quadword repeated to every element ({1to8} at 512 bits). VPORD is the same with doublewords; unmasked, the two give the same bits. VPANDD shows what the EVEX forms add and how GCC 14 and Clang 23 choose among such names.

On Zen 5, vporq zmm0{k1}, zmm31, qword bcst [mem] with 1 in memory and A0h in the low byte of K1 set bit 0 of quadwords 5 and 7 of ZMM31 into ZMM0 and left the other six of ZMM0 alone. With a merging mask the destination keeps what the mask leaves out, so OR under a mask can set bits in only some elements of a vector.

In compiled code#

GCC 14 at -O2 with -march=x86-64-v4 uses VPORQ for long long data and also where the element size does not matter:

• Setting bits. q[i] |= 1ULL << 63 becomes a VPBROADCASTQ of the constant before the loop and one VPORQ per eight elements.
• Bytes. s[i] = t[i] | 0x20 over char arrays, which turns ASCII letters to lower case, is a VPBROADCASTB and VPORQ on zmm registers, since an OR without a mask has no element size. With -mavx512f alone GCC drops to VEX VPOR on ymm registers for that loop, and Clang 23 uses VPORQ on zmm registers.
• Testing a whole array. Whether any long long is nonzero is an OR of everything, done in the loop by VPTERNLOGQ on two vectors at a time; GCC folds the result with VEXTRACTI64X4 and VEXTRACTI64X2, each followed by VPORQ.

Clang 23 with -march=x86-64-v4 uses VORPS and, for _mm512_mask_or_epi64, a masked VORPD instead, which selects the same quadwords; with -mavx512f it emits VPORQ for both. For a byte constant such as _mm512_set1_epi8(0x20) it builds one quadword and ORs with a {1to8} operand.

AMD’s Zen 5 latency spreadsheet gives the EVEX row of VPORQ one cycle and four per cycle on any of the four vector pipes. Zen 5’s 6 recorded cases cover the register and memory forms, broadcast included, at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = zmm2.q[i] | src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPORQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD

All 686 AVX10.1 instructions