Instruction
VPPERM
Picks each byte of the result from 32 bytes of two sources and optionally inverts, reverses or replaces it, by selectors in a third; XOP.
An AMD extension: Intel processors do not have this instruction.
- Extensions
- Forms
- 3 (3 XOP)
- Data
- Intel XED v2026.08.23
In the optimization guide
What the optimization guide says about VPPERM, a line per claim. Each links to the claim in the guide, with its sources and where they differ.
Bulldozer to Excavator
- Vectors and floating point: XOP adds integer instructions of three and four operands: VPPERM, which selects bytes from two registers, VPCMOV, a bitwise select, rotates, shifts by a count per element, compares into masks and multiply-accumulates.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPPERM xmm, xmm, m128, xmm
VPPERM_XMMdq_XMMdq_MEMdq_XMMdq | XOP.128.NP.08.W0 A3 /r /is4 | XOP |
VPPERM xmm, xmm, xmm, xmm
VPPERM_XMMdq_XMMdq_XMMdq_XMMdq | XOP.128.NP.08.W0 A3 /r /is4XOP.128.NP.08.W1 A3 /r /is4 | XOP |
VPPERM xmm, xmm, xmm, m128
VPPERM_XMMdq_XMMdq_XMMdq_MEMdq | XOP.128.NP.08.W1 A3 /r /is4 | XOP |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Example control bytes in xmm4 (element 0 on the right, in hex). No processor here has XOP: the example was not run, but worked out by the pseudocode below.
With the example control bytes, result bytes 15 to 0: a9, a0, b12, a14, b1, ~a3, a7, b8, FF, a10, b4, a5, 0, b15, a2, b3.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 11 & 1:
fault(UD) # CPUID: no XOP
for i in range(16):
c = src4.b[i] # the control of byte i
a = xmm2.b[c & 15]
b = src3.b[c & 15]
x = b if c & 16 else a
op = c >> 5
if op in (1, 3):
x ^= 0xFF # inverted
if op in (2, 3):
r = 0
for k in range(8): # its bits reversed
r |= (x >> k & 1) << (7 - k)
x = r
elif op == 4:
x = 0
elif op == 5:
x = 0xFF
elif op == 6:
x = 0xFF if x >> 7 else 0 # its top bit everywhere
elif op == 7:
x = 0 if x >> 7 else 0xFF # inverted
xmm1.b[i] = x
# xmm1 is zeroed from bit 128 upRun on AMD Zen 5 (EPYC 9645): 3 cases. Its cases ran where CPUID reported no XOP, and every one raised an exception.
Operands
| Operand | Kind | Action |
|---|---|---|
VPPERM xmm, xmm, xmm/m128, xmm | ||
xmm | explicit | write |
xmm | explicit | read |
xmm/m128 | explicit | read |
xmm | explicit | read |
VPPERM xmm, xmm, xmm, m128 | ||
xmm | explicit | write |
xmm | explicit | read |
xmm | explicit | read |
m128 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPPERM, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_perm_epi8
__m128i _mm_perm_epi8(__m128i __A, __m128i __B, __m128i __C) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
XOP | XOP | Bulldozer, Piledriver |
More XOP instructions
- VPERMIL2PS
- VPHADDBD
- VPHADDBQ
- VPHADDBW
- VPHADDDQ
- VPHADDUBD
- VPHADDUBQ
- VPHADDUBW
- VPHADDUDQ
- VPHADDUWD
- VPHADDUWQ
- VPHADDWD
- VPHADDWQ
- VPHSUBBW
- VPHSUBDQ
- VPHSUBWD
- VPMACSDD
- VPMACSDQH
- VPMACSDQL
- VPMACSSDD
- VPMACSSDQH
- VPMACSSDQL
- VPMACSSWD
- VPMACSSWW
- VPMACSWD
- VPMACSWW
- VPMADCSSWD
- VPMADCSWD
- VPROTB
- VPROTD
- VPROTQ
- VPROTW
- VPSHAB
- VPSHAD
- VPSHAQ
- VPSHAW
- VPSHLB
- VPSHLD
- VPSHLQ
- VPSHLW
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.