Extensions
Forms
3 (3 XOP)
Data
Intel XED v2026.08.23

In the optimization guide

What the optimization guide says about VPPERM, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Bulldozer to Excavator

  • Vectors and floating point: XOP adds integer instructions of three and four operands: VPPERM, which selects bytes from two registers, VPCMOV, a bitwise select, rotates, shifts by a count per element, compares into masks and multiply-accumulates.

Forms

Every encoding of VPPERM that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPPERM xmm, xmm, m128, xmm VPPERM_XMMdq_XMMdq_MEMdq_XMMdqXOP.128.NP.08.W0 A3 /r /is4XOP
VPPERM xmm, xmm, xmm, xmm VPPERM_XMMdq_XMMdq_XMMdq_XMMdqXOP.128.NP.08.W0 A3 /r /is4
XOP.128.NP.08.W1 A3 /r /is4
XOP
VPPERM xmm, xmm, xmm, m128 VPPERM_XMMdq_XMMdq_XMMdq_MEMdqXOP.128.NP.08.W1 A3 /r /is4XOP

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Permute bytes from two sources: each byte of the result is the byte of xmm2 or, with bit 4 of its control byte in xmm4 set, of xmm3 that bits 3:0 number, as bits 7:5 say: as it is (000b), inverted (001b), its bits reversed (010b), both (011b), 0 (100b), all ones (101b), its sign bit in every bit (110b) or that inverted (111b).
VPPERM with example control bytesWith the example control bytes, result bytes 15 to 0: a9, a0, b12, a14, b1, ~a3, a7, b8, FF, a10, b4, a5, 0, b15, a2, b3.13021F8005140AA0180723110E1C0009xmm4or m1280235791014146811121315xmm2ab3b15b4b8b1b12a2a5a10a7a14a0a90FF~a3xmm10256791011131413481215xmm3or m128b

Example control bytes in xmm4 (element 0 on the right, in hex). No processor here has XOP: the example was not run, but worked out by the pseudocode below.

With the example control bytes, result bytes 15 to 0: a9, a0, b12, a14, b1, ~a3, a7, b8, FF, a10, b4, a5, 0, b15, a2, b3.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 11 & 1:
    fault(UD)                    # CPUID: no XOP
for i in range(16):
    c = src4.b[i]                # the control of byte i
    a = xmm2.b[c & 15]
    b = src3.b[c & 15]
    x = b if c & 16 else a
    op = c >> 5
    if op in (1, 3):
        x ^= 0xFF                # inverted
    if op in (2, 3):
        r = 0
        for k in range(8):       # its bits reversed
            r |= (x >> k & 1) << (7 - k)
        x = r
    elif op == 4:
        x = 0
    elif op == 5:
        x = 0xFF
    elif op == 6:
        x = 0xFF if x >> 7 else 0  # its top bit everywhere
    elif op == 7:
        x = 0 if x >> 7 else 0xFF  # inverted
    xmm1.b[i] = x
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 3 cases. Its cases ran where CPUID reported no XOP, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPPERM xmm, xmm, xmm/m128, xmm
xmmexplicitwrite
xmmexplicitread
xmm/m128explicitread
xmmexplicitread
VPPERM xmm, xmm, xmm, m128
xmmexplicitwrite
xmmexplicitread
xmmexplicitread
m128explicitread

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPPERM, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_perm_epi8 __m128i _mm_perm_epi8(__m128i __A, __m128i __B, __m128i __C)

VPPERM xmm, xmm, xmm, xmm XOP.128 -mxop

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
XOP

XOP
CPUID.80000001H:ECX[11] XOP

Bulldozer, Piledriver

More XOP instructions

All 55 XOP instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.