VPROLD

VPROLD rotates each doubleword left by the count in its immediate: the bits that leave at the top come back in at the bottom. It is AVX-512F’s, with masking, a broadcast source and the xmm and ymm forms under AVX512VL; before it, SSE and AVX2 had no vector rotate, and only AMD’s XOP had one, VPROTD. VPRORD rotates right, which is the same as rotating left by 32 minus the count; VPROLVD takes a count per element from a register, and VPROLQ rotates quadwords.

The count#

Only the low 5 bits of the immediate count, so a count of 33 rotates by 1 and 32 by nothing. The cases recorded on Zen 5 show this with 21h: 7FFFFFFFh became FFFFFFFEh and 80000000h became 1, as a rotate by one gives. ROL on a 32-bit register masks its count the same way, but there the count can come from CL; here it is fixed in the instruction.

From shifts to one instruction#

Without AVX-512, a rotate is two shifts and an OR. For a loop over a uint32_t array computing (x << 7) | (x >> 25), GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 emit VPSLLD, VPSRLD and VPOR, except that Clang turns rotations by 8 and 16, which move whole bytes, into one VPSHUFB. With -march=x86-64-v4 both compilers recognize the pattern and emit VPROLD for every count, on zmm registers in GCC and on ymm in Clang.

Ciphers and hashes built from 32-bit words rotate a lot. Intel’s optimization guide shows SM4 encryption with AVX-512 and GFNI, where each round’s linear step XORs a word with its rotations by 2, 10, 18 and 24, four VPROLDs combined with VPTERNLOGD (Example 19-2).

AMD’s Zen 5 guide lists VPROLD as one macro-op with a latency of two cycles: the same latency as an EVEX shift by an immediate followed by an OR, one cycle each, in one instruction instead of three. The VEX shifts of the -march=x86-64-v3 code take two cycles each.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = rol(src2.d[i], imm8, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPROLD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ

All 686 AVX10.1 instructions