VPROLQ

VPROLQ rotates each quadword left by the count in its immediate. It is the quadword form of VPROLD, whose page covers the shifts and OR it replaces; VPRORQ rotates right and VPROLVQ takes a count per element from a register. Only the low 6 bits of the immediate count, so 64 rotates by nothing and 65 by one.

Recorded on Zen 5#

• With 41h, vprolq zmm9{k7}, zmm9, 0x41 rotated by one: 8000000000000000h became 1 and 0Fh became 1Eh.
• With 40h, vprolq zmm1{k7}, qword bcst [mem], 0x40 wrote the broadcast 7FFFFFFFFFFFFFFFh unchanged to the elements K7 selects.
• With 7Fh, a count of 63, the rotate is one to the right: vprolq xmm5{k5}{z}, qword bcst [mem], 0x7f turned a broadcast 0Fh into 8000000000000007h.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile (x << 7) | (x >> 57) over a uint64_t array to VPROLQ, GCC on ZMM and Clang on YMM registers, and also the rotate right (x >> 7) | (x << 57), as VPROLQ by 57. A step of SHA-512’s message schedule, a rotate right by 1 XORed with one by 8 and a shift right by 7, becomes two VPROLQs by 63 and 56, a VPSRLQ and a VPTERNLOGQ with 96h, the XOR of three. For a count held in a variable, Clang uses VPROLVQ and GCC two shifts and an OR. Given a count of 70 in _mm512_rol_epi64, GCC passes 70 to the assembler and Clang reduces it to 6.

AMD’s Zen 5 latency spreadsheet gives VPROLQ what it gives VPROLD: 2 cycles and two per cycle on pipes FP0 and FP1. Zen 5’s 6 recorded cases cover the register, memory and broadcast forms at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = rol(src2.q[i], imm8, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPROLQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD

All 686 AVX10.1 instructions