VPROLVD

VPROLVD rotates each doubleword of its first source left by the count in the matching doubleword of the second source, which may be a broadcast doubleword. It is the variable form of VPROLD, whose page covers the rotate and the shifts it replaces, and the doubleword form of VPROLVQ. VPRORVD rotates right, and VPSLLVD is the shift with per-element counts. Only the low 5 bits of each count matter, so a count of 32 leaves the element as it is, where VPSLLVD would give zero. It needs AVX512F, plus AVX512VL below 512 bits, and takes a write mask.

Recorded on Zen 5#

• Counts modulo 32. {evex} vprolvd xmm17, xmm30, xmm2 rotated 1 by 1 into 2 and 1 by 20h into 1, and FFFFFFFFh stayed FFFFFFFFh for the counts 1Fh and 21h.
• Large counts. In vprolvd ymm5{k3}, ymm5, ymmword ptr [mem], a count of 80000000h left 7FFFFFFFh unchanged, 1Fh turned it into BFFFFFFFh, a rotate right by one, and 3 turned 80000000h into 4.
• Merging. In the same case, the elements that K3 does not select kept their values, and the register was cleared from bit 256 up.

In compiled code#

At -O2 with -march=x86-64-v4, Clang 23 compiles (x[i] << s) | (x[i] >> ((32 - s) & 31)) with s = c[i] & 31 over uint32_t arrays to VPROLVD on YMM registers, with the counts c[i] straight from memory and no AND, since the instruction reduces them itself. GCC 14 keeps the AND, VPSLLVD, VPSRLVD and an OR on ZMM registers. Both compile _mm512_rolv_epi32 to one VPROLVD.

AMD’s Zen 5 latency spreadsheet gives VPROLVD one macro-op with 2 cycles, two per cycle on pipes FP0 and FP1, as VPROLVQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = zmm2.d[i]
        b = src3.d[i]
        zmm1.d[i] = rol(a, b, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPROLVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ

All 686 AVX10.1 instructions