VPRORVD

VPRORVD rotates each doubleword of its first source right by the count in the matching doubleword of the second source, which may be a broadcast doubleword. Only the low 5 bits of each count matter. A rotate right by n is a rotate left by 32 - n, so it adds nothing that VPROLVD cannot do with other counts; it saves the subtraction when the counts are given for the right. It is the variable form of VPRORD, and VPRORVQ rotates quadwords. It needs AVX512F, plus AVX512VL below 512 bits, and takes a write mask.

Recorded on Zen 5#

• Plain rotates. {evex} vprorvd xmm14, xmm8, xmm29 turned 7FFFFFFFh rotated by 16 into FFFF7FFFh and 80000000h rotated by 3 into 10000000h, and left 7FFFFFFFh as it was for a count of 0.
• Counts modulo 32. In vprorvd ymm0{k3}{z}, ymm31, ymm16, the count FFFFFFFFh rotated 1 right by 31 into 2, 1Fh rotated 8 into 10h, and 80000000h left 1 as it was. Elements 2 and 4, which K3 does not select, became zero.
• Merging. vprorvd zmm1{k1}, zmm2, zmm3 wrote only the five elements K1 selects and kept the other eleven.

In compiled code#

At -O2 with -march=x86-64-v4, Clang 23 compiles (x[i] >> s) | (x[i] << ((32 - s) & 31)) with s = c[i] & 31 over uint32_t arrays to VPRORVD on YMM registers, and broadcasts a single count for the whole loop to use VPRORVD as well. GCC 14 keeps VPSRLVD, VPSLLVD and an OR, or VPSRLD and VPSLLD for the single count. Both compile _mm512_rorv_epi32 to one VPRORVD.

AMD’s Zen 5 latency spreadsheet gives VPRORVD one macro-op with 2 cycles, two per cycle on pipes FP0 and FP1, as the left rotates.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = zmm2.d[i]
        b = src3.d[i]
        zmm1.d[i] = ror(a, b, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPRORVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB

All 686 AVX10.1 instructions