VPRORVQ

VPRORVQ rotates each quadword of its first source right by the count in the matching quadword of the second source, which may be a broadcast quadword. Only the low 6 bits of each count matter, so 40h rotates by nothing and 7Fh by 63, a rotate left by one. It is the variable form of VPRORQ and the right-hand partner of VPROLVQ, whose page covers the shifts it replaces; VPRORVD rotates doublewords. It needs AVX512F, plus AVX512VL below 512 bits, and takes a write mask.

Recorded on Zen 5#

• Counts modulo 64. In vprorvq zmm9{k2}, zmm9, zmm14, 1 rotated right by 1 became 8000000000000000h, 7FFFFFFFFFFFFFFFh rotated by 7Fh became FFFFFFFFFFFFFFFEh, and -1 rotated by 41h stayed -1.
• Halves swapped. With a broadcast count of 20h, vprorvq zmm1{k1}, zmm2, qword bcst [mem] turned 7FFFFFFFFFFFFFFFh into FFFFFFFF7FFFFFFFh and 8000000000000000h into 80000000h in the two elements K1 selects, and left the other six alone.
• Register form. {evex} vprorvq xmm7, xmm12, xmm7 turned 1 rotated by 3 into 2000000000000000h and cleared XMM7 above bit 127.

In compiled code#

At -O2 with -march=x86-64-v4, Clang 23 compiles (x[i] >> s) | (x[i] << ((64 - s) & 63)) with s = c[i] & 63 over uint64_t arrays to VPRORVQ on YMM registers, with the counts read straight from memory. GCC 14 keeps VPSRLVQ, VPSLLVQ and an OR on ZMM registers. Both compile _mm512_rorv_epi64 to one VPRORVQ.

AMD’s Zen 5 latency spreadsheet gives VPRORVQ one macro-op with 2 cycles, two per cycle on pipes FP0 and FP1, as VPROLVQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = zmm2.q[i]
        b = src3.q[i]
        zmm1.q[i] = ror(a, b, 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPRORVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD

All 686 AVX10.1 instructions