Extensions
Forms
5 (5 XOP)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPROTQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPROTQ xmm, m128, imm8 VPROTQ_XMMdq_MEMdq_IMMbXOP.128.NP.08.W0 C3 /r ibXOP
VPROTQ xmm, xmm, imm8 VPROTQ_XMMdq_XMMdq_IMMbXOP.128.NP.08.W0 C3 /r ibXOP
VPROTQ xmm, m128, xmm VPROTQ_XMMdq_MEMdq_XMMdqXOP.128.NP.09.W0 93 /rXOP
VPROTQ xmm, xmm, xmm VPROTQ_XMMdq_XMMdq_XMMdqXOP.128.NP.09.W0 93 /r
XOP.128.NP.09.W1 93 /r
XOP
VPROTQ xmm, xmm, m128 VPROTQ_XMMdq_XMMdq_MEMdqXOP.128.NP.09.W1 93 /rXOP

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.VPROTQ xmm, xmm/m128, imm8
VPROTQ: element by elementResult quadword i comes from quadword i of xmm2. Result quadwords 1 to 0: r1, r0.01xmm2or m128ar0r1xmm1

Result quadword i comes from quadword i of xmm2. Result quadwords 1 to 0: r1, r0.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.VPROTQ xmm, xmm/m128, xmm VPROTQ xmm, xmm, m128
VPROTQ: element by elementResult quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: r1, r0.01xmm3or m128b

Result quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VPROTQ xmm, xmm/m128, imm8
features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 11 & 1:
    fault(UD)  # CPUID: no XOP
for i in range(2):
    xmm1.q[i] = rol(src2.q[i], imm8, 64)
# a negative count rotates right
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no XOP, and every one raised an exception.

VPROTQ xmm, xmm/m128, xmm VPROTQ xmm, xmm, m128
features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 11 & 1:
    fault(UD)  # CPUID: no XOP
for i in range(2):
    a = src2.q[i]
    b = src3.q[i]
    xmm1.q[i] = rol(a, b, 64)
# a negative count rotates right
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 3 cases. Its cases ran where CPUID reported no XOP, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPROTQ xmm, xmm/m128, imm8
xmmexplicitwrite
xmm/m128explicitread
imm8explicitread
VPROTQ xmm, xmm/m128, xmm
xmmexplicitwrite
xmm/m128explicitread
xmmexplicitread
VPROTQ xmm, xmm, m128
xmmexplicitwrite
xmmexplicitread
m128explicitread

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPROTQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_rot_epi64 __m128i _mm_rot_epi64(__m128i __A, __m128i __B)

VPROTQ xmm, xmm, xmm XOP.128 -mxop

_mm_roti_epi64 __m128i _mm_roti_epi64(__m128i A, const int N)

VPROTQ xmm, xmm, imm8 XOP.128 -mxop

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
XOP

XOP
CPUID.80000001H:ECX[11] XOP

Bulldozer, Piledriver

More XOP instructions

All 55 XOP instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.