Instruction
VPROTW
Rotates each word left or right by a signed count from an immediate or a register or memory; XOP.
An AMD extension: Intel processors do not have this instruction.
- Extensions
- Forms
- 5 (5 XOP)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPROTW xmm, m128, imm8
VPROTW_XMMdq_MEMdq_IMMb | XOP.128.NP.08.W0 C1 /r ib | XOP |
VPROTW xmm, xmm, imm8
VPROTW_XMMdq_XMMdq_IMMb | XOP.128.NP.08.W0 C1 /r ib | XOP |
VPROTW xmm, m128, xmm
VPROTW_XMMdq_MEMdq_XMMdq | XOP.128.NP.09.W0 91 /r | XOP |
VPROTW xmm, xmm, xmm
VPROTW_XMMdq_XMMdq_XMMdq | XOP.128.NP.09.W0 91 /rXOP.128.NP.09.W1 91 /r | XOP |
VPROTW xmm, xmm, m128
VPROTW_XMMdq_XMMdq_MEMdq | XOP.128.NP.09.W1 91 /r | XOP |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
VPROTW xmm, xmm/m128, imm8Result word i comes from word i of xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.
VPROTW xmm, xmm/m128, xmm VPROTW xmm, xmm, m128Result word i comes from word i of xmm2 and xmm3. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
VPROTW xmm, xmm/m128, imm8features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 11 & 1:
fault(UD) # CPUID: no XOP
for i in range(8):
xmm1.w[i] = rol(src2.w[i], imm8, 16)
# a negative count rotates right
# xmm1 is zeroed from bit 128 upRun on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no XOP, and every one raised an exception.
VPROTW xmm, xmm/m128, xmm VPROTW xmm, xmm, m128features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 11 & 1:
fault(UD) # CPUID: no XOP
for i in range(8):
a = src2.w[i]
b = src3.w[i]
xmm1.w[i] = rol(a, b, 16)
# a negative count rotates right
# xmm1 is zeroed from bit 128 upRun on AMD Zen 5 (EPYC 9645): 3 cases. Its cases ran where CPUID reported no XOP, and every one raised an exception.
Operands
| Operand | Kind | Action |
|---|---|---|
VPROTW xmm, xmm/m128, imm8 | ||
xmm | explicit | write |
xmm/m128 | explicit | read |
imm8 | explicit | read |
VPROTW xmm, xmm/m128, xmm | ||
xmm | explicit | write |
xmm/m128 | explicit | read |
xmm | explicit | read |
VPROTW xmm, xmm, m128 | ||
xmm | explicit | write |
xmm | explicit | read |
m128 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPROTW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_rot_epi16
__m128i _mm_rot_epi16(__m128i __A, __m128i __B) |
|
_mm_roti_epi16
__m128i _mm_roti_epi16(__m128i A, const int N) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
XOP | XOP | Bulldozer, Piledriver |
More XOP instructions
- VPERMIL2PS
- VPHADDBD
- VPHADDBQ
- VPHADDBW
- VPHADDDQ
- VPHADDUBD
- VPHADDUBQ
- VPHADDUBW
- VPHADDUDQ
- VPHADDUWD
- VPHADDUWQ
- VPHADDWD
- VPHADDWQ
- VPHSUBBW
- VPHSUBDQ
- VPHSUBWD
- VPMACSDD
- VPMACSDQH
- VPMACSDQL
- VPMACSSDD
- VPMACSSDQH
- VPMACSSDQL
- VPMACSSWD
- VPMACSSWW
- VPMACSWD
- VPMACSWW
- VPMADCSSWD
- VPMADCSWD
- VPPERM
- VPROTB
- VPROTD
- VPROTQ
- VPSHAB
- VPSHAD
- VPSHAQ
- VPSHAW
- VPSHLB
- VPSHLD
- VPSHLQ
- VPSHLW
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.