VPSADBW

VPSADBW is PSADBW in VEX and EVEX encodings: per quadword, the absolute differences of eight pairs of unsigned bytes are added, and the total, at most 2040, goes to bits 15:0 of the quadword with the rest cleared. The PSADBW page explains the instruction and its two classic uses, block matching and summing bytes against a zero register. What changes here is the width and the encoding:

• Three operands. The destination is separate from both sources, so neither input is lost, and a memory operand needs no alignment.
• Wider vectors. AVX2 gives four sums in a YMM register and AVX512BW eight in a ZMM register. The VEX.128 form clears the register from bit 128 up, as every VEX and EVEX form clears it above its width.
• No write mask. The EVEX forms take neither a mask nor a broadcast: unlike most AVX-512 integer instructions, VPSADBW has no {k} operand at any width, and its intrinsics have no _mask variants. What EVEX adds is the registers from XMM16 to XMM31, such as XMM29 and YMM24 in the cases recorded on Zen 5.

In compiled code#

For s += abs(p[i] - q[i]) over uint8_t arrays of a constant length of 1024, GCC 14 at -O2 emits one VPSADBW per 32 bytes with -march=x86-64-v3 and per 64 bytes with -march=x86-64-v4, and adds the quadword sums with VPADDD. Clang 23 loads eight bytes at a time with VMOVQ and uses the 128-bit form on them, under either target. When the length is a variable, GCC keeps the loop scalar.

The zero-register trick is how Clang 23 finishes a population count without hardware support for vectors: for __builtin_popcountll over a uint64_t array with -march=x86-64-v3 or -march=x86-64-v4 (neither includes AVX512_VPOPCNTDQ), it counts the bits of each byte with two VPSHUFB lookups, one per nibble, and then VPSADBW against zero adds the eight byte counts of each quadword, which VPADDQ accumulates. GCC 14 uses the scalar POPCNT instead.

VDBPSADBW of AVX512BW is the instruction that does take a mask: it computes sums of four bytes, after shuffling the second source.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    x = 0
    for j in range(8 * i, 8 * i + 8):
        x += abs(zmm2.b[j] - src3.b[j])
    zmm1.q[i] = x
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSADBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLW
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ

All 253 AVX instructions

More AVX2 instructions

• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD

All 138 AVX2 instructions

More AVX10.1 instructions

• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW

All 686 AVX10.1 instructions