x86-64.net

Instruction

VPSADBW

Sums the absolute differences of unsigned bytes over each group of eight, giving one 16-bit sum per quadword.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPSADBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSADBW xmm, xmm, m128 VPSADBW_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG F6 /rAVX
VPSADBW xmm, xmm, xmm VPSADBW_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG F6 /rAVX
VPSADBW ymm, ymm, m256 VPSADBW_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG F6 /rAVX2
VPSADBW ymm, ymm, ymm VPSADBW_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG F6 /rAVX2
VPSADBW xmm, xmm, xmm VPSADBW_XMMu16_XMMu8_XMMu8_AVX512EVEX.128.66.0F.WIG F6 /rAVX10.1 or AVX512BW + AVX512VL
VPSADBW xmm, xmm, m128 VPSADBW_XMMu16_XMMu8_MEMu8_AVX512EVEX.128.66.0F.WIG F6 /rAVX10.1 or AVX512BW + AVX512VL
VPSADBW ymm, ymm, ymm VPSADBW_YMMu16_YMMu8_YMMu8_AVX512EVEX.256.66.0F.WIG F6 /rAVX10.1 or AVX512BW + AVX512VL
VPSADBW ymm, ymm, m256 VPSADBW_YMMu16_YMMu8_MEMu8_AVX512EVEX.256.66.0F.WIG F6 /rAVX10.1 or AVX512BW + AVX512VL
VPSADBW zmm, zmm, zmm VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512EVEX.512.66.0F.WIG F6 /rAVX10.1 or AVX512BW
VPSADBW zmm, zmm, m512 VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512EVEX.512.66.0F.WIG F6 /rAVX10.1 or AVX512BW

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSADBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_sad_epu8 __m128i _mm_sad_epu8(__m128i __a, __m128i __b)

VPSADBW xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm256_sad_epu8 __m256i _mm256_sad_epu8(__m256i __a, __m256i __b)

VPSADBW ymm, ymm, ymm VEX.256 -mavx2

_mm512_sad_epu8 __m512i _mm512_sad_epu8(__m512i __A, __m512i __B)

VPSADBW zmm, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.