VPSCATTERDD

VPSCATTERDD stores the doublewords of a vector to scattered addresses: element i goes to a base plus element i of an index vector, a signed 32-bit integer, times a scale of 1, 2, 4 or 8. It is d[idx[i]] = s[i] in one instruction, the store that mirrors VPGATHERDD. Scatters exist only in AVX-512; AVX2 has gathers but no scatter. As with the gathers (see VGATHERDPS), a mask register chooses the elements, each mask bit is cleared as its element is stored, and the whole mask register is zero at the end; a fault partway leaves the elements below the faulting one stored and their bits cleared, so that the instruction can resume.

Repeated indices#

Two elements may name the same address. Intel’s manual guarantees that overlapping stores happen in element order, so the highest element wins, and lets the processor skip the earlier stores to an address written again. Stores that do not overlap may happen in any order. In a case recorded on Zen 5 whose 16 indices took only two values, memory kept the values of elements 13 and 15, the last ones with each index.

That order is what lets compilers vectorize a plain scatter loop: in d[idx[i]] = s[i] the scalar loop’s last write wins too. GCC 14 and Clang 23 at -O2 turn it into VPSCATTERDD for -march=x86-64-v4, with an all-ones mask made by KXNORW or KXNORB; for znver4 and znver5 Clang uses zmm registers, and GCC keeps the loop scalar. A read-modify-write such as a histogram, h[idx[i]] += 1, is different: a gather, an addition and a scatter lose the counts of repeated indices, which is the problem VPCONFLICTD solves.

Cost#

A scatter is one store per element. Intel’s optimization guide warns against using it for sequential elements, which one vector store writes, and in its example of a conversion followed by a scatter, measures the hardware scatter only slightly ahead of a software sequence of permutes and scalar stores, 1.53 against 1.48 times scalar code (Section 17.11.1, Table 17-4). AMD’s Zen 5 guide lists every scatter as microcoded.

VPSCATTERQD takes 64-bit indices, VPSCATTERDQ and VPSCATTERQQ store quadwords, and VSCATTERDPS singles.

In the optimization guide

What the optimization guide says about VPSCATTERDD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Scatters store one element at a time; Intel replaces short-stride scatters by permutes and stores, and they are microcode on Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = mem.index.sd[i] * mem.scale
        store(mem.base + a, 32, zmm2.d[i])
k1.write(0)  # all of it

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

scatter; write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSCATTERDD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW

All 686 AVX10.1 instructions