VPSCATTERDQ

VPSCATTERDQ stores the quadwords of a vector to scattered addresses: element i goes to a base plus element i of an index vector, a signed 32-bit integer, times a scale. With 64-bit data and 32-bit indices, the index register is half as wide as the data: 8 quadwords of a ZMM register take their indices from a YMM register, 4 and 2 from an XMM register. It is the quadword form of VPSCATTERDD, whose page explains the mask that is cleared as elements are stored, the order of repeated indices and the cost, and the store that mirrors VPGATHERDQ.

Recorded on Zen 5#

• Negative indices. vpscatterdq qword ptr [base + ymm14*8]{k2}, zmm7, with 59h in the low byte of K2, stored elements 0, 3, 4 and 6 at indices -4, 1, 4 and 2, 32 bytes below the base for element 0.
• The whole mask is cleared. That K2 held C1660194AD895859h and ended as 0, all 64 bits, not just the eight that select elements.
• Nothing selected. With the low two bits of K3 clear, the XMM form stored nothing and still cleared K3.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 vectorize d[idx[i]] = s[i] over int64_t data and int indices into VPSCATTERDQ. GCC uses ZMM registers: one 16-index load serves two scatters, the upper eight indices brought down with VSHUFI32X4, and each scatter gets a copy of an all-ones mask made once by KXNORB, since the scatter clears its own. Clang scatters four quadwords at a time from YMM registers with a fresh KXNORW before each, and with -march=znver5 eight at a time from ZMM registers, where GCC leaves the loop scalar. With a condition, if (s[i] > 0), the compare’s mask is the scatter’s mask in both. A loop of unknown length stays scalar in both. _mm512_i32scatter_epi64 is KXNORB and VPSCATTERDQ in both.

AMD’s Zen 5 latency spreadsheet lists VPSCATTERDQ as microcoded, as every scatter.

In the optimization guide

What the optimization guide says about VPSCATTERDQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Scatters store one element at a time; Intel replaces short-stride scatters by permutes and stores, and they are microcode on Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = mem.index.sd[i] * mem.scale
        store(mem.base + a, 64, zmm2.q[i])
k1.write(0)  # all of it

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

scatter; write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSCATTERDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD

All 686 AVX10.1 instructions