VPSCATTERQD

VPSCATTERQD stores doublewords to scattered addresses: element i goes to a base plus element i of an index vector, a signed 64-bit integer, times a scale of 1, 2, 4 or 8. Eight 64-bit indices in a ZMM register place the eight doublewords of a YMM register, and the YMM and XMM index forms place four or two from an XMM register. It is the 64-bit-index form of VPSCATTERDD, whose page explains the mask that is cleared as elements are stored, the order of repeated indices and the cost. VPGATHERQD is the load it mirrors, VSCATTERQPS the same store under a floating-point name, and VPSCATTERQQ the form with quadword data. It came with AVX512F.

Recorded on Zen 5#

• Repeated indices. In vpscatterqd dword ptr [base + zmm9*1]{k3}, ymm4, with 76h in the low byte of K3, three selected elements, 1, 4 and 5, had the index -8, and two, 2 and 6, the index 56. Each address ended with the doubleword of the highest of its elements, 5 and 6, as the order from element 0 upward implies.
• Below the base. The YMM index form stored its two selected elements at indices -6 and -10 times 4, 24 and 40 bytes below the base.
• Mask. The mask register ended as 0 in every case, all 64 bits, including the XMM form that had no element selected and stored nothing.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile id[lx[i]] = is[i], int data with long indices, to VPSCATTERQD, GCC with ZMM indices, Clang with YMM indices and XMM data; with -march=znver5 Clang moves to ZMM indices and GCC keeps the loop scalar. For x86-64-v4, _mm512_i64scatter_epi32 is KXNORB and VPSCATTERQD in both.

AMD’s Zen 5 latency spreadsheet lists VPSCATTERQD as microcoded, as every scatter.

In the optimization guide

What the optimization guide says about VPSCATTERQD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Scatters store one element at a time; Intel replaces short-stride scatters by permutes and stores, and they are microcode on Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = mem.index.sq[i] * mem.scale
        store(mem.base + a, 32, ymm2.d[i])
k1.write(0)  # all of it

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

scatter; write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSCATTERQD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ

All 686 AVX10.1 instructions