VPSCATTERQQ

VPSCATTERQQ stores the quadwords of a vector to scattered addresses: element i goes to a base plus element i of an index vector, a signed 64-bit integer, times a scale of 1, 2, 4 or 8. Index and data have the same width, so 8 quadwords of a ZMM register take 8 indices from a ZMM register, and the YMM and XMM forms 4 and 2. It is the 64-bit-index form of VPSCATTERDQ, and VPSCATTERDD’s page explains the mask that is cleared as elements are stored, the order of repeated indices and the cost. VPGATHERQQ is the load it mirrors, and VSCATTERQPD the same store under a floating-point name. It came with AVX512F.

Recorded on Zen 5#

• Overlapping, unaligned stores. With a scale of 1 and indices 23, 38 and -23, five selected elements wrote eight bytes each at unaligned offsets, two of them to addresses already written by an earlier element; at both, the bytes of the later element were left.
• Below the base. In the XMM form, index -8 times 8 stored element 1 at 64 bytes below the base.
• Mask. In every case the mask register ended as 0, all 64 bits, and in the YMM form the element that K3 left out stored nothing.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile d[ix[i]] = s[i], with int64_t data and long indices, to VPSCATTERQQ. GCC scatters from ZMM registers, copying an all-ones mask made once by KXNORB with KMOVB before each scatter; Clang scatters from YMM registers with a fresh KXNORW before each, and with -march=znver5 from ZMM registers, where GCC leaves the loop scalar. _mm512_i64scatter_epi64 is KXNORB and VPSCATTERQQ in both, except with GCC’s -march=znver5, which loads the all-ones byte from memory with KMOVB instead.

AMD’s Zen 5 latency spreadsheet lists VPSCATTERQQ as microcoded, as every scatter.

In the optimization guide

What the optimization guide says about VPSCATTERQQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Scatters store one element at a time; Intel replaces short-stride scatters by permutes and stores, and they are microcode on Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = mem.index.sq[i] * mem.scale
        store(mem.base + a, 64, zmm2.q[i])
k1.write(0)  # all of it

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

scatter; write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSCATTERQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ

All 686 AVX10.1 instructions