VPSHAD instruction (XOP)

Forms

Every encoding of VPSHAD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPSHAD xmm, m128, xmm` VPSHAD_XMMdq_MEMdq_XMMdq	`XOP.128.NP.09.W0 9A /r`	XOP
`VPSHAD xmm, xmm, xmm` VPSHAD_XMMdq_XMMdq_XMMdq	`XOP.128.NP.09.W0 9A /r` `XOP.128.NP.09.W1 9A /r`	XOP
`VPSHAD xmm, xmm, m128` VPSHAD_XMMdq_XMMdq_MEMdq	`XOP.128.NP.09.W1 9A /r`	XOP

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = cpuid_leaf(0x80000001, 0)[2]
if not r >> 11 & 1:
    fault(UD)                    # CPUID: no XOP
for i in range(4):
    c = src3.sb[4 * i]           # doubleword i's low byte, signed
    if abs(c) >= 32:
        xmm1.d[i] = UNDEFINED    # AMD's manual says nothing
    elif c >= 0:
        xmm1.d[i] = src2.sd[i] << c
    else:
        xmm1.d[i] = src2.sd[i] >> -c  # sign bits in
# AMD's manual has the count modulo the width
# for VPSHAW, VPSHLD, VPSHAQ and VPSHLQ
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 4 cases. Its cases ran where CPUID reported no XOP, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPSHAD xmm, xmm/m128, xmm`
`xmm`	explicit	write
`xmm/m128`	explicit	read
`xmm`	explicit	read
`VPSHAD xmm, xmm, m128`
`xmm`	explicit	write
`xmm`	explicit	read
`m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHAD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sha_epi32` `__m128i _mm_sha_epi32(__m128i __A, __m128i __B)`	`VPSHAD xmm, xmm, xmm` XOP.128 -mxop

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`XOP` XOP	XOP `CPUID.80000001H:ECX[11]` XOP	Bulldozer, Piledriver

More XOP instructions

All 55 XOP instructions