VPSHLDD

VPSHLDD is a funnel shift per doubleword: it joins each element of the first source above the matching element of the second, shifts the 64-bit pair left by the immediate, taken modulo 32, and keeps the upper 32 bits. The bits shifted out of the first source are replaced by the top bits of the second, as SHLD does for general-purpose registers. VPSHRDD is the right-shifting counterpart, and VPSHLDVD takes per-element counts from a register.

It belongs to AVX512_VBMI2, which x86-64-v4 does not include: GCC 14 and Clang 23 need -mavx512vbmi2 (or a -march that has it) before they emit it.

Uses#

• Rotates of words. With the same register in both sources a funnel shift is a rotate. AVX-512F rotates doublewords and quadwords with VPROLD, but has no word rotate; Clang 23 at -O2 compiles (a << 3) | (a >> 13) on uint16_t vectors to vpshldw zmm0, zmm0, zmm0, 3, while GCC 14 keeps two shifts and an OR.
• Shifting a long bit string. To shift a whole register, or an array, by a few bits, each element needs the top bits of its lower neighbour. VALIGND lines the neighbours up and VPSHLDD merges them: Clang vectorizes d[i] = (a[i+1] << 5) | (a[i] >> 27) that way, and with intrinsics both compilers shift a 512-bit register left by 5 bits as a zeroed register, a VALIGND and a VPSHLDD.
• Combining shifted fields from two registers, the pattern (a << n) | (b >> (32 - n)), which Clang recognizes and emits as one VPSHLDD; GCC emits it only for the intrinsic.

AMD’s Zen 5 guide lists VPSHLDD and its word and right-shift kin as one macro-op with a latency of 2 cycles, the same as VPROLD. VPSHLDQ and VPSHLDW work on quadwords and words.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = zmm2.d[i]
        b = src3.d[i]
        x = a << 32 | b
        zmm1.d[i] = x << (imm8 & 31) >> 32
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHLDD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMULUDQ
• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD

All 686 AVX10.1 instructions