VPSHLDQ

VPSHLDQ is the quadword form of VPSHLDD, whose page explains the funnel shift and its uses: each quadword of the first source is joined above the matching quadword of the second, the 128-bit pair is shifted left by the immediate, taken modulo 64, and the upper 64 bits are kept. It is what SHLD does to two 64-bit registers, for up to eight pairs at once, and VPSHRDQ is its right-shifting twin. It belongs to AVX512_VBMI2, which -march=znver5 enables and x86-64-v4 does not.

Recorded on Zen 5#

• Counts modulo 64. With 40h, a count of 64, vpshldq xmm14, xmm8, xmm29, 0x40 returned the first source, 0 and 1, and ignored the second. With 7Fh, 63, 8000000000000000h over 8000000000000000h gave 4000000000000000h, bit 0 of the first above bits 63:1 of the second.
• The second source fills from below. By 1, 7FFFFFFFFFFFFFFFh over 1 gave FFFFFFFFFFFFFFFEh, and 0Fh over 1 gave 1Eh; by 32, 7FFFFFFFFFFFFFFFh over the same value gave FFFFFFFF7FFFFFFFh.
• Masks and broadcasts. The cases cover zeroing and merging masks and a broadcast quadword as second source.

In compiled code#

With -march=znver5, Clang 23 at -O2 compiles (a[i] << 13) | (b[i] >> 51) over uint64_t arrays to VPSHLDQ by 13 with b as the memory operand, and the same for VPSHRDQ’s right shifts, as that page shows; GCC 14 keeps VPSLLQ, VPSRLQ and VPORQ, and emits VPSHLDQ only for _mm512_shldi_epi64, masked or not. With one array in both places, (a[i] << 13) | (a[i] >> 51), both use the rotate VPROLQ. Shifting a long bit string left by 5, each element taking the top bits of the one below, Clang lines up the neighbours with VALIGNQ and uses VPSHLDQ, while GCC loads the array twice at offsets 8 bytes apart and shifts and ORs. Shifting a 128-bit XMM value left by 5 bits is VPSLLDQ by 8 and one VPSHLDQ in both.

AMD’s Zen 5 latency spreadsheet gives VPSHLDQ 2 cycles and two per cycle on pipes FP0 and FP1, as VPSHLDD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = zmm2.q[i]
        b = src3.q[i]
        x = a << 64 | b
        zmm1.q[i] = x << (imm8 & 63) >> 64
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHLDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPOPCNTB
• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ

All 686 AVX10.1 instructions