VPSHLDVD

VPSHLDVD is the variable form of VPSHLDD: each doubleword of the destination is joined above the matching doubleword of the first source, the 64-bit pair is shifted left by a count taken from the matching element of the second source, and the upper 32 bits are kept. The VPSHLDD page explains the funnel shift and its uses with a fixed count; here every element can have its own.

Three inputs, one of them the destination#

The destination supplies the upper half and receives the result, as with VPTERNLOGD. In the intrinsic _mm512_shldv_epi32(a, b, c), a is the upper half and the register that gets overwritten, b the lower half and c the counts; a value of a still needed afterwards costs a copy.

Counts wrap at 32#

Only bits 4:0 of each count matter. A count of 0 returns the upper half unchanged, and larger counts wrap. In the cases recorded on Zen 5, a count of 7Fh acted as 31, and counts of 80h (broadcast) and 80000000h as 0, returning the first operand. The plain variable shifts disagree: VPSLLVD and VPSRLVD give zero for any count above 31, and VPROLVD, the variable rotate, wraps like VPSHLDVD. Code that moves from one to the other must keep counts in range or rely on the right rule.

In compiled code#

The instruction needs AVX512_VBMI2, which x86-64-v4 lacks; Zen 5 runs it, as the recorded cases show, and -march=znver5 enables it. At -O2 with that target:

• Clang 23 compiles a loop of n ? (a[i] << n) | (b[i] >> (32 - n)) : a[i], with n = c[i] & 31, to VPSHLDVD, under a write mask that reproduces the test for zero. GCC 14 keeps VPSLLVD, VPSRLVD and VPORD.
• For a variable rotate of uint16_t values, which AVX-512 has no instruction for, Clang emits VPSHLDVW with the same register as both halves, where GCC uses two shifts and an OR; for uint32_t Clang uses VPROLVD.
• The intrinsics give the instruction in both compilers.

VPSHRDVD shifts right, and VPSHLDVQ works on quadwords. AMD’s Zen 5 guide lists VPSHLDVD as one macro-op with a latency of two cycles, like VPSHLDD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = zmm1.d[i]
        b = zmm2.d[i]
        c = src3.d[i]
        x = a << 32 | b
        zmm1.d[i] = x << (c & 31) >> 32
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHLDVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPOPCNTD
• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW

All 686 AVX10.1 instructions