VPSHLDVQ

VPSHLDVQ is the quadword form of VPSHLDVD: each quadword of the destination is joined above the matching quadword of the first source, the 128-bit pair is shifted left by the count in the matching quadword of the second source, taken modulo 64, and the upper 64 bits are written back to the destination. VPSHLDVD’s page explains the three inputs, VPSHLDQ is the form with one immediate count, and VPSHRDVQ shifts right. The counts can come as one broadcast quadword. It belongs to AVX512_VBMI2, which x86-64-v4 lacks and -march=znver5 enables.

Recorded on Zen 5#

• Counts modulo 64. In vpshldvq zmm17{k5}, zmm30, zmm2, a count of 8000000000000001h acted as 1, turning 1 above all ones into 3, 7FFFFFFFFFFFFFFFh acted as 63, turning all ones above 1 into 8000000000000000h, and 80h acted as 0.
• A broadcast count. 799F3A5C8D26D1AFh, 47 modulo 64, shifted 1 above all ones to 0000FFFFFFFFFFFFh: bit 0 rose to bit 47, and the top 47 bits of the lower half filled the bits below it.

In compiled code#

At -O2 with -march=znver5, Clang 23 compiles s ? (hi[i] << s) | (lo[i] >> (64 - s)) : hi[i] with uint64_t s = c[i] & 63 to VPSHLDVQ, keeping the test of s against zero with VPTESTNMQ, and the branch-free (hi[i] << s) | ((lo[i] >> 1) >> (63 - s)) to VPSHLDVQ alone; a rotate of one array becomes VPROLVQ. GCC 14 keeps VPSLLVQ, VPSRLVQ and an OR. _mm512_shldv_epi64(a, b, c) is one VPSHLDVQ in both.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP0 or FP1 and 2 cycles, two per cycle, as for VPSHLDQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = zmm1.q[i]
        b = zmm2.q[i]
        c = src3.q[i]
        x = a << 64 | b
        zmm1.q[i] = x << (c & 63) >> 64
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHLDVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPOPCNTQ
• VPOPCNTW
• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW

All 686 AVX10.1 instructions