VPSHLDW

VPSHLDW is the word form of VPSHLDD, whose page explains the funnel shift: each word of the first source is joined above the matching word of the second, the 32-bit pair is shifted left by the immediate and the upper 16 bits are kept. Only bits 3:0 of the immediate count. Like the rest of AVX512_VBMI2 it is not part of x86-64-v4; -march=znver5 includes it.

Recorded on Zen 5#

• vpshldw xmm9, xmm9, xmm14, 0x1 shifted 7FFFh up by one and filled the low bit from FFFFh, giving FFFFh, and turned 8000h above 8000h into 0001h: the top bit of the first source fell out, the top bit of the second came in.
• Counts wrap at 16. With 10h, vpshldw zmm24{k3}, zmm3, [mem], 0x10 wrote the words of ZMM3 unchanged to the elements K3 selects. With FFh, acting as 15, {evex} vpshldw ymm0, ymm31, [mem], 0xff kept only the low bit of each word of YMM31, now on top, above the high 15 bits of the memory word: 8000h above FFFFh gave 7FFFh.

In compiled code#

Built with -march=znver5 at -O2, Clang 23 uses VPSHLDW for 16-bit rotates and funnel shifts written in C: over uint16_t arrays, (a[i] << 3) | (a[i] >> 13) becomes vpshldw zmm0, zmm0, zmm0, 3 and (a[i] << 3) | (b[i] >> 13) a VPSHLDW that reads b from memory. GCC 14 compiles both to VPSLLW, VPSRLW and VPORQ, and emits VPSHLDW only for the intrinsic _mm512_shldi_epi16. It passes a count of 16 or 17 to the assembler as written; Clang returns the first operand unchanged for 16, with no instruction, and reduces 17 to 1.

AVX-512 has no word rotate, so the funnel shift with one register twice is the one-instruction way to rotate words.

AMD’s Zen 5 latency spreadsheet gives VPSHLDW 2 cycles and two per cycle on pipes FP0 and FP1, as VPSHLDD. Zen 5’s 6 recorded cases cover the register and memory forms at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.w[i]
        b = src3.w[i]
        x = a << 16 | b
        zmm1.w[i] = x << (imm8 & 15) >> 16
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHLDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPORD
• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ

All 686 AVX10.1 instructions