VPSHRDD

VPSHRDD is the right-shifting twin of VPSHLDD, whose page explains funnel shifts and their uses. Per doubleword it joins the second source above the first, shifts the 64-bit pair right by the immediate, taken modulo 32, and keeps the lower 32 bits: the bits shifted out of the first source are replaced by the low bits of the second, as SHRD does for general-purpose registers.

Which half is which#

Both instructions keep the bits of the first source and fill in from the second, but the halves swap places: VPSHLDD puts the first source on top, VPSHRDD at the bottom. A right shift by n is therefore the same as a left shift by 32 - n with the sources exchanged. The cases recorded on Zen 5 show the edges:

• an immediate of 0 returns the first source unchanged;
• 1Fh gives the second source shifted left by one, with the top bit of the first below it: 7FFFFFFFh under 00000001h gave 00000002h;
• with the same register as both sources it is a rotate right, and an immediate of 21h acted as 1, turning 00000001h into 80000000h and 7FFFFFFFh into BFFFFFFFh.

In compiled code#

The instruction needs AVX512_VBMI2; -march=znver5 enables it, x86-64-v4 does not. At -O2 with that target:

• GCC 14 compiles _mm512_shrdi_epi32(a, b, 5) to vpshrdd zmm0, zmm0, zmm1, 5.
• Clang 23 compiles the same intrinsic to vpshldd zmm0, zmm1, zmm0, 27, the equivalent left shift. It does so for every _shrdi_ intrinsic, which is why they are listed on the VPSHLDD page and this page lists none.
• For (a >> 5) | (b << 27) on vectors of uint32_t, Clang emits the same VPSHLDD; GCC keeps two shifts and an OR, and for a loop of (a[i] >> 5) | (a[i+1] << 27), scalar SHLD.

VPSHRDVD takes a count per element, and VPSHRDQ and VPSHRDW work on quadwords and words.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = zmm2.d[i]
        b = src3.d[i]
        x = b << 32 | a
        zmm1.d[i] = x >> (imm8 & 31)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPORQ
• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD

All 686 AVX10.1 instructions