x86-64.net

Instruction

VPSHRDQ

Joins each quadword of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPSHRDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSHRDQ xmm {k}{z}, xmm, xmm, imm8 VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512EVEX.128.66.0F3A.W1 73 /r ibAVX10.1 or AVX512_VBMI2 + AVX512VL
VPSHRDQ xmm {k}{z}, xmm, m128/m64bcst, imm8 VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512EVEX.128.66.0F3A.W1 73 /r ibAVX10.1 or AVX512_VBMI2 + AVX512VL
VPSHRDQ ymm {k}{z}, ymm, ymm, imm8 VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512EVEX.256.66.0F3A.W1 73 /r ibAVX10.1 or AVX512_VBMI2 + AVX512VL
VPSHRDQ ymm {k}{z}, ymm, m256/m64bcst, imm8 VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512EVEX.256.66.0F3A.W1 73 /r ibAVX10.1 or AVX512_VBMI2 + AVX512VL
VPSHRDQ zmm {k}{z}, zmm, zmm, imm8 VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512EVEX.512.66.0F3A.W1 73 /r ibAVX10.1 or AVX512_VBMI2
VPSHRDQ zmm {k}{z}, zmm, m512/m64bcst, imm8 VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512EVEX.512.66.0F3A.W1 73 /r ibAVX10.1 or AVX512_VBMI2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_VBMI2_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_VBMI2 + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[6] AVX512_VBMI2
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VBMI2_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_VBMI2 + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[6] AVX512_VBMI2
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VBMI2_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_VBMI2
CPUID.(EAX=07H,ECX=0):ECX[6] AVX512_VBMI2

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.