VPSHRDQ

VPSHRDQ is the quadword form of VPSHRDD, whose page explains which source goes where, and the right-shifting twin of VPSHLDQ: each quadword of the second source is joined above the matching quadword of the first, the 128-bit pair is shifted right by the immediate, taken modulo 64, and the low 64 bits are kept. It is what SHRD does to two 64-bit registers, for up to eight pairs at once. It belongs to AVX512_VBMI2, which -march=znver5 enables and x86-64-v4 does not, and takes masking and a broadcast quadword.

Recorded on Zen 5#

• Counts modulo 64. FFh and 7Fh both shifted by 63: 1 under FFFFFFFFFFFFFFFFh gave FFFFFFFFFFFFFFFEh, the second source moved up by one with bit 63 of the first below it, and 8000000000000000h under 7FFFFFFFFFFFFFFFh gave all ones.
• A count of 0 returned the first source: in vpshrdq ymm14{k3}, ymm8, ymmword ptr [mem], 0x0 every selected element came from YMM8.
• One register twice is a rotate. vpshrdq ymm24{k5}{z}, ymm3, ymm3, 0x7f turned 8 into 10h, a rotate right by 63, which is a rotate left by one.

In compiled code#

The compilers prefer the left-shifting form. With -march=znver5, Clang 23 at -O2 compiles (lo[i] >> 13) | (hi[i] << 51) over uint64_t arrays, and the intrinsic _mm512_shrdi_epi64(a, b, 13) too, to VPSHLDQ by 51 with the sources swapped; GCC 14 keeps the loop as VPSRLQ, VPSLLQ and VPORQ, and emits VPSHRDQ only for the intrinsic, masked or not. Shifting a long bit string right by 13, with each element’s high bits taken from the next one, Clang lines up the neighbours with VALIGNQ and again uses VPSHLDQ, while GCC leaves that loop scalar.

AMD’s Zen 5 latency spreadsheet gives VPSHRDQ 2 cycles and two per cycle on pipes FP0 and FP1, as VPSHRDD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = zmm2.q[i]
        b = src3.q[i]
        x = b << 64 | a
        zmm1.q[i] = x >> (imm8 & 63)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPROLD
• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ

All 686 AVX10.1 instructions