VPSHRDVD

VPSHRDVD is the variable form of VPSHRDD: per doubleword, the matching element of the first source is joined above the destination’s, the 64-bit pair is shifted right by a count from the second source, and the lower 32 bits are kept. Its left-shifting twin, VPSHLDVD, explains the three-input form and why only bits 4:0 of a count matter.

The destination is the lower half#

In both variable funnel shifts the destination holds the half whose bits survive the shift, but here that is the lower half: the result is the destination shifted right, filled from the top with the low bits of the first source. In _mm512_shrdv_epi32(a, b, c), a is the lower half and the register written, b the upper half and c the counts. With the same register as destination and first source it is a rotate right per element: on Zen 5, a broadcast count of 0C337E85h, which is 5 modulo 32, turned 80000000h into 04000000h and 7FFFFFFFh into FBFFFFFFh.

Counts wrap at 32, as the recorded cases show: a count of 80h acted as 0 and returned the destination unchanged, and 7Fh acted as 31, so 7FFFFFFFh under 00000001h became 00000002h. The plain shift VPSRLVD gives zero for any count above 31 instead.

In compiled code#

At -O2 with -march=znver5, which enables AVX512_VBMI2:

• Clang 23 compiles a loop of s ? (a[i] >> s) | (b[i] << (32 - s)) : a[i], with s = c[i] & 31, to VPSHRDVD under a write mask that stands for the test of s against zero, and uses scalar SHRD for the last elements.
• GCC 14 keeps that loop scalar, with SHRX and SHLX.
• _mm512_shrdv_epi32 gives VPSHRDVD in both compilers. Unlike the immediate form, which Clang rewrites as a left shift, the variable form stays a right shift.

VPSHRDVQ and VPSHRDVW work on quadwords and words.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = zmm1.d[i]
        b = zmm2.d[i]
        c = src3.d[i]
        x = b << 32 | a
        zmm1.d[i] = x >> (c & 31)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHRDVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPROLQ
• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW

All 686 AVX10.1 instructions