VPSHRDVQ

VPSHRDVQ is the quadword form of VPSHRDVD: per element, the quadword of the first source is joined above the destination’s, the 128-bit pair is shifted right by the count in the matching quadword of the second source, taken modulo 64, and the low 64 bits are written back to the destination. VPSHRDVD’s page explains why the destination is the lower half, and VPSHRDQ is the form with one immediate count. It belongs to AVX512_VBMI2, which -march=znver5 enables and x86-64-v4 does not.

Recorded on Zen 5#

• A funnel. {evex} vpshrdvq xmm14, xmm8, xmm29 shifted 0 under 1 right by one: element 1 became 8000000000000000h, bit 0 of the first source moved into bit 63.
• Counts modulo 64. A count of 7FFFFFFFFFFFFFFFh acted as 63: with 8 in both halves, vpshrdvq ymm5{k2}, ymm5, ymmword ptr [mem] gave 10h, and a count of 8000000000000000h acted as 0 and left the element as it was.
• One register three times is a rotate right by the element itself: in vpshrdvq zmm5{k4}, zmm5, zmm5, 7Fh became FEh, a rotate right by 63, and 1 became 8000000000000000h.

In compiled code#

At -O2 with -march=znver5, Clang 23 compiles s ? (lo[i] >> s) | (hi[i] << (64 - s)) : lo[i] with uint64_t s = c[i] & 63 to VPSHRDVQ on ZMM registers, keeping a test of s against zero with VPTESTNMQ, and the branch-free (lo[i] >> s) | ((hi[i] << 1) << (63 - s)) to VPSHRDVQ alone. With a 32-bit s it keeps the plain shifts, and GCC 14 does in every case, with VPSRLVQ, VPSLLVQ and an OR. _mm512_shrdv_epi64(a, b, c) is one VPSHRDVQ in both, a the lower half and the register written.

AMD’s Zen 5 latency spreadsheet gives one macro-op, 2 cycles, two per cycle on pipes FP0 and FP1, as for VPSHRDQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = zmm1.q[i]
        b = zmm2.q[i]
        c = src3.q[i]
        x = b << 64 | a
        zmm1.q[i] = x >> (c & 63)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHRDVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPROLVD
• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW

All 686 AVX10.1 instructions