VPSHRDVW

VPSHRDVW is the word form of VPSHRDVD: each word of the first source is joined above the matching word of the destination, the 32-bit pair is shifted right by the count in the matching word of the second source, and the lower 16 bits are written back to the destination. VPSHRDVD’s page explains why the destination is the lower half; VPSHLDVW shifts left and VPSHRDW takes one immediate count. Only bits 3:0 of each count matter, and the second source has no broadcast form. It belongs to AVX512_VBMI2, which x86-64-v4 lacks and -march=znver5 enables.

Recorded on Zen 5#

• A funnel. In {evex} vpshrdvw xmm24, xmm3, xmm3, a destination word of 0 under 007Fh, shifted right by 15 (7Fh modulo 16), gave 00FEh: seven bits of the upper half came down into the lower one.
• A rotate. With one register three times, as in vpshrdvw zmm5{k1}, zmm5, zmm5, each word is rotated right by itself: 7FFFh, a count of 15, became FFFEh, a rotate left by one.

In compiled code#

At -O2 with -march=znver5, Clang 23 compiles a loop of variable right rotates of uint16_t, (h[i] >> n) | (h[i] << ((16 - n) & 15)) with n = c[i] & 15, to VPSHRDVW with the same register as both halves; GCC 14 uses VPSRLVW, VPSLLVW and an OR. A shift right of two uint16_t arrays joined into 32 bits is widened to doublewords by both. _mm512_shrdv_epi16(a, b, c) is one VPSHRDVW, a the lower half and the register written.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP0 or FP1 and 2 cycles, two per cycle, the figures of every VBMI2 funnel shift.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.w[i]
        b = zmm2.w[i]
        c = src3.w[i]
        x = b << 16 | a
        zmm1.w[i] = x >> (c & 15)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHRDVW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPROLVQ
• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD

All 686 AVX10.1 instructions