VPSHRDW

VPSHRDW is the word form of VPSHRDD and the right-shifting twin of VPSHLDW: each word of the second source is joined above the matching word of the first, the 32-bit pair is shifted right by the immediate and the low 16 bits are kept. Only bits 3:0 of the immediate count, so the bits shifted out of the first source are replaced by up to 15 low bits of the second. It belongs to AVX512_VBMI2, which -march=znver5 enables and x86-64-v4 does not; VPSHRDVW takes a count per word.

Recorded on Zen 5#

• One bit. In vpshrdw ymm1{k3}{z}, ymm2, ymm3, 0x1, 0000h under 0001h gave 8000h and 7FFFh under 0001h gave BFFFh: the low bit of the second source became the top bit of the result.
• Fifteen bits. With 0Fh, or FFh acting as 15, the result is the second source shifted left by one, with the top bit of the first below it: in {evex} vpshrdw ymm17, ymm30, [mem], 0xf, 8000h under 0001h gave 0003h and 0001h under FFFFh gave FFFEh.
• Counts wrap at 16. {evex} vpshrdw xmm5, xmm5, xmm5, 0x10 left the words of XMM5 as they were, and an immediate of 0 wrote the first source unchanged to the words the mask selected.

In compiled code#

Clang 23 never emits it. Built with -march=znver5 at -O2, it compiles _mm512_shrdi_epi16(a, b, 3) to vpshldw zmm0, zmm1, zmm0, 13, the same funnel shift written as a left shift with the sources swapped, and over uint16_t arrays it turns the rotate (a[i] >> 3) | (a[i] << 13) and the funnel shift (a[i] >> 3) | (b[i] << 13) into VPSHLDW as well. GCC 14 emits VPSHRDW for the intrinsic and compiles both loops to VPSRLW, VPSLLW and VPORQ.

AMD’s Zen 5 latency spreadsheet gives VPSHRDW 2 cycles and two per cycle on pipes FP0 and FP1, as VPSHRDD. Zen 5’s 6 recorded cases cover the register and memory forms at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.w[i]
        b = src3.w[i]
        x = b << 16 | a
        zmm1.w[i] = x >> (imm8 & 15)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPRORD
• VPRORQ
• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ

All 686 AVX10.1 instructions