x86-64.net

Instruction

VPSHUFB

Rearranges bytes within each 128-bit lane using an index byte per result, which zeroes the byte when its top bit is set.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPSHUFB is PSHUFB in VEX and EVEX encodings: each byte of the second source picks a byte of the first, and a selector with bit 7 set gives zero. The PSHUFB page covers the selectors and the common uses; what changes here is the width. AVX2 extends it to 256 bits and AVX512BW to 512 bits with byte masking, but as 2 or 4 independent 128-bit shuffles: a selector reaches only the 16 bytes of its own lane. A case recorded on Zen 5 shows it: the selector 02h at byte 16 of a ymm register took byte 18, DBh, and not byte 2, D3h.

Living with lanes

Anything that stays inside 16 bytes fits directly. Swapping the bytes of every doubleword never crosses a lane, so for d[i] = __builtin_bswap32(a[i]) GCC 14 and Clang 23 at -O2 emit one VPSHUFB per vector, on ymm registers for -march=x86-64-v3 and on zmm for znver5. A lookup table has to be repeated in each lane, which VBROADCASTI128 does from a 16-byte table in memory.

What crosses lanes needs a second instruction. Reversing all 32 bytes of a ymm register takes VPSHUFB and a lane swap, VPERMQ in Clang and VPERM2I128 in GCC; with AVX512_VBMI, as for znver5, both use one VPERMB instead.

Nibble lookups

The table form is how vector code counts bits without a population count instruction. Clang vectorizes d[i] = __builtin_popcount(a[i]) on bytes for x86-64-v3 and x86-64-v4 as two VPSHUFB lookups in a 16-entry table of bit counts, one with the low nibbles (VPAND with 0Fh) and one with the high nibbles (VPSRLW by 4, then VPAND), added with VPADDB; GCC 14 keeps the loop scalar with POPCNT. Where the processor has AVX512_BITALG, as for znver5, both compilers use VPOPCNTB instead, and VPOPCNTD for doublewords.

AMD’s Zen 5 guide lists VPSHUFB as one macro-op with a latency of 2 cycles at every width, against 4 and 5 cycles for the ymm and zmm forms of VPERMB, so staying in lanes still pays off.

In the optimization guide

What the optimization guide says about VPSHUFB, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

  • Shuffles and lane crossing: Lane-crossing permutes such as VPERMD take longer than in-lane shuffles such as VPSHUFB, and LLVM treats them as slow on Zen. sources differ

Forms

Every encoding of VPSHUFB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSHUFB xmm, xmm, m128 VPSHUFB_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.WIG 00 /rAVX
VPSHUFB xmm, xmm, xmm VPSHUFB_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.WIG 00 /rAVX
VPSHUFB ymm, ymm, m256 VPSHUFB_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.WIG 00 /rAVX2
VPSHUFB ymm, ymm, ymm VPSHUFB_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.WIG 00 /rAVX2
VPSHUFB xmm {k}{z}, xmm, xmm VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512EVEX.128.66.0F38.WIG 00 /rAVX10.1 or AVX512BW + AVX512VL
VPSHUFB xmm {k}{z}, xmm, m128 VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512EVEX.128.66.0F38.WIG 00 /rAVX10.1 or AVX512BW + AVX512VL
VPSHUFB ymm {k}{z}, ymm, ymm VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512EVEX.256.66.0F38.WIG 00 /rAVX10.1 or AVX512BW + AVX512VL
VPSHUFB ymm {k}{z}, ymm, m256 VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512EVEX.256.66.0F38.WIG 00 /rAVX10.1 or AVX512BW + AVX512VL
VPSHUFB zmm {k}{z}, zmm, zmm VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512EVEX.512.66.0F38.WIG 00 /rAVX10.1 or AVX512BW
VPSHUFB zmm {k}{z}, zmm, m512 VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512EVEX.512.66.0F38.WIG 00 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128no mask		xmm, xmm, xmmymm, ymm, m256
ymm {k}{z}, ymm, m256no mask		ymm, ymm, ymm
xmm {k}{z}, xmm, xmmno mask
ymm {k}{z}, ymm, ymmno mask		xmm {k}{z}, xmm, xmmwith a mask, zeroing
ymm {k}{z}, ymm, ymmwith a mask, zeroing		xmm {k}{z}, xmm, m128with a mask, zeroingymm {k}{z}, ymm, m256with a mask, zeroingzmm {k}{z}, zmm, zmmno maskzmm {k}{z}, zmm, zmmwith a mask, zeroingzmm {k}{z}, zmm, m512no maskzmm {k}{z}, zmm, m512with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell, Skylake7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake-SP7 / 1p51 / 1p58 / 1p51 / 1p51 / 1p57 / 1p58 / 1p51 / 1p51 / 1p58 / 1p58 / 1p5
Ice Lake7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p151 / 0.5p157 / 0.5p158 / 0.5p151 / 1p51 / 1p58 / 1p58 / 1p5
Alder Lake8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p15
Sapphire Rapids8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p153 / 0.5p1511 / 0.5p1511 / 0.5p151 / 1p53 / 1p59 / 1p511 / 1p5
Lunar Lake7 / 2V2 V31 / 0.5V2 V38 / 2.33V2 V31 / 0.5V2 V3
Piledriver8 / 1.5FPU1 FPXBR3 / 1FPU1 FPXBR
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 1FPU1 FPU21 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 48 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP22 / 11FP0 FP12 / 12FP0 FP18 / 0.5FP1 FP28 / 0.5FP1 FP22 / 1FP0 FP12 / 1FP0 FP18 / 1FP1 FP28 / 1FP1 FP2
Jaguar7 / 2FPU0 FPU1 VALU0 VALU12 / 2FPU0 FPU1 VALU0 VALU1
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 2874; AMD 58455, row 1228).
  2. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 2875; AMD 58455, row 384).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Shuffle bytes by index: each byte of the result is the byte of xmm2 that the index byte in the same place numbers, within the lane; an index with bit 7 set gives 0.
VPSHUFB with an example index vectorWith the example indices, result bytes 15 to 0: a11, unchanged (bit 14 of k1 is 0), a2, a10, a5, 0, a14, a1, a9, a15, a0, a7, a12, a12, 0, a3.0123567910111214154813xmm2a1111111111111110k1a3a12a12a7a0a15a9a1a14a5a10a2a1100xmm1380CC70F91E805A26Bxmm3index

Example index vector in xmm3 (element 0 on the right, in hex); only its low 4 bits and bit 7 count. The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

With the example indices, result bytes 15 to 0: a11, unchanged (bit 14 of k1 is 0), a2, a10, a5, 0, a14, a1, a9, a15, a0, a7, a12, a12, 0, a3.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:  # 1 without a write mask
        x = src3.b[i]
        j = i - i % 16 + (x & 15)
        if x & 0x80:
            zmm1.b[i] = 0
        else:
            zmm1.b[i] = zmm2.b[j]
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPSHUFB xmm, xmm, xmm/m128 VPSHUFB ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPSHUFB xmm {k}{z}, xmm, xmm/m128 VPSHUFB ymm {k}{z}, ymm, ymm/m256 VPSHUFB zmm {k}{z}, zmm, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHUFB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_shuffle_epi8 __m128i _mm_shuffle_epi8(__m128i __a, __m128i __b)

VPSHUFB xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_shuffle_epi8 __m128i _mm_mask_shuffle_epi8(__m128i __W, __mmask16 __U, __m128i __A, __m128i __B)

VPSHUFB xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_shuffle_epi8 __m128i _mm_maskz_shuffle_epi8(__mmask16 __U, __m128i __A, __m128i __B)

VPSHUFB xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_shuffle_epi8 __m256i _mm256_shuffle_epi8(__m256i __a, __m256i __b)

VPSHUFB ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_shuffle_epi8 __m256i _mm256_mask_shuffle_epi8(__m256i __W, __mmask32 __U, __m256i __A, __m256i __B)

VPSHUFB ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_shuffle_epi8 __m256i _mm256_maskz_shuffle_epi8(__mmask32 __U, __m256i __A, __m256i __B)

VPSHUFB ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_shuffle_epi8 __m512i _mm512_shuffle_epi8(__m512i __A, __m512i __B)

VPSHUFB zmm, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_shuffle_epi8 __m512i _mm512_mask_shuffle_epi8(__m512i __W, __mmask64 __U, __m512i __A, __m512i __B)

VPSHUFB zmm {k}, zmm, zmm EVEX.512 -mavx512bw

_mm512_maskz_shuffle_epi8 __m512i _mm512_maskz_shuffle_epi8(__mmask64 __U, __m512i __A, __m512i __B)

VPSHUFB zmm {k}{z}, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-422 (PSHUFB)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.