VPSHUFBITQMB

VPSHUFBITQMB gathers single bits into a mask register. Each byte of the second source is an index: byte i picks one bit of quadword i / 8 of the first source, and that bit becomes bit i of the destination mask. Eight index bytes share each quadword, so the 64 bytes of a zmm register pick 8 arbitrary bits from each of the 8 quadwords, 64 mask bits in all. It belongs to AVX512_BITALG with VPOPCNTB and VPOPCNTW, and its intrinsic is _mm512_bitshuffle_epi64_mask(data, indices).

Indices and the mask#

Only the low 6 bits of an index count, 0 to 63 within its quadword; the two above are ignored. In a case recorded on Zen 5 with the quadword 8000000000000001h, the index FFh took bit 63, as 3Fh does. The data is the first source, always a register, and the indices are the operand that may be in memory, without embedded broadcast.

The result is a mask, so the write mask works as it does for VPCMPD: a bit the write mask leaves out becomes 0 instead of keeping its old value, which makes k1{k2} the AND of k2 and the gathered bits, and the bits above 16 or 32 of the xmm and ymm forms are cleared.

Uses#

• A bit permutation of a 64-bit value: broadcast it to all eight quadwords with VPBROADCASTQ, gather with 64 indices that list the source bit of each result bit, and move the mask to a general register with KMOVQ. Any permutation, repetition or selection of bits takes these three instructions, where PEXT can only pack selected bits in their original order.
• Eight bit fields at once: with different data in each quadword, one instruction tests a chosen bit in each of 64 bitmaps, or picks the same eight positions out of eight words, and the mask can drive masked stores or VPCOMPRESSB directly.

Neither GCC 14 nor Clang 23 forms the instruction from plain C; it comes from the intrinsics.

AMD’s Zen 5 guide lists VPSHUFBITQMB with a latency of 3, 4 and 6 cycles for xmm, ymm and zmm sources; the register forms are one macro-op and the memory forms two.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):         # bit i, of quadword i // 8
    if k2[i]:                    # 1 without a write mask
        c = src3.b[i] & 63       # the bit it takes
        k1[i] = zmm2.q[i // 8] >> c & 1
    else:
        k1[i] = 0                # never merged
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHUFBITQMB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPRORVD
• VPRORVQ
• VPSADBW
• VPSCATTERDD
• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD

All 686 AVX10.1 instructions