x86-64.net

Instruction

VPSHUFD

Rearranges doublewords within each 128-bit lane as an immediate selects.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPSHUFD is PSHUFD in VEX and EVEX encodings: an immediate with two bits per result element picks the source doubleword for each position. The PSHUFD page explains the immediate and its common values. The wider forms do not widen the shuffle: they apply the same four selectors to each 128-bit lane, so a result element can only come from its own lane. A case recorded on Zen 5 shows it: vpshufd ymm8, ymm15, 0x83 filled element 0 with source element 3 and element 4 with source element 7, not 3.

What the newer encodings add:

  • Any address. The memory source needs no alignment, unlike the legacy form’s 16 bytes, and the VEX.128 form clears the destination register above bit 127.
  • Masks and a broadcast (EVEX: AVX512F, or AVX10.1). A write mask selects the doublewords written, with merging or zeroing. A broadcast source is legal but makes every element the same, so the immediate no longer matters: on Zen 5, vpshufd zmm9{k4}, dword bcst [mem], 0xa8 wrote the one doubleword wherever K4 had a 1.

In compiled code

GCC 14 at -O2 compiles _mm256_shuffle_epi32(x, 0x1B) to VPSHUFD with -march=x86-64-v3, and the 512-bit intrinsic likewise with -march=x86-64-v4. Clang 23 emits VSHUFPS for both, with x as both of its sources, which picks the same elements in each lane. Reversing all eight doublewords crosses lanes, so it takes VPERMD and an index vector instead: GCC 14 uses VPERMD, Clang 23 the float equivalent VPERMPS.

AMD’s latency spreadsheet for Zen 5 gives VPSHUFD one cycle and four per cycle at every width, on any of the four vector pipes. Zen 5’s 10 recorded cases cover every form, with immediates such as 59h, 83h and EDh.

Forms

Every encoding of VPSHUFD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSHUFD xmm, m128, imm8 VPSHUFD_XMMdq_MEMdq_IMMbVEX.128.66.0F.WIG 70 /r ibAVX
VPSHUFD xmm, xmm, imm8 VPSHUFD_XMMdq_XMMdq_IMMbVEX.128.66.0F.WIG 70 /r ibAVX
VPSHUFD ymm, m256, imm8 VPSHUFD_YMMqq_MEMqq_IMMbVEX.256.66.0F.WIG 70 /r ibAVX2
VPSHUFD ymm, ymm, imm8 VPSHUFD_YMMqq_YMMqq_IMMbVEX.256.66.0F.WIG 70 /r ibAVX2
VPSHUFD zmm {k}{z}, zmm, imm8 VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512EVEX.512.66.0F.W0 70 /r ibAVX10.1 or AVX512F
VPSHUFD zmm {k}{z}, m512/m32bcst, imm8 VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.512.66.0F.W0 70 /r ibAVX10.1 or AVX512F
VPSHUFD xmm {k}{z}, xmm, imm8 VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512EVEX.128.66.0F.W0 70 /r ibAVX10.1 or AVX512F + AVX512VL
VPSHUFD xmm {k}{z}, m128/m32bcst, imm8 VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.128.66.0F.W0 70 /r ibAVX10.1 or AVX512F + AVX512VL
VPSHUFD ymm {k}{z}, ymm, imm8 VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512EVEX.256.66.0F.W0 70 /r ibAVX10.1 or AVX512F + AVX512VL
VPSHUFD ymm {k}{z}, m256/m32bcst, imm8 VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.256.66.0F.W0 70 /r ibAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, m128, imm8
xmm {k}{z}, m128/m32bcst, imm8		xmm, xmm, imm8
xmm {k}{z}, xmm, imm8
ymm {k}{z}, ymm, imm8		ymm, m256, imm8
ymm {k}{z}, m256/m32bcst, imm8		ymm, ymm, imm8zmm {k}{z}, zmm, imm8zmm {k}{z}, m512/m32bcst, imm8
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell, Skylake7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake-SP7 / 1p51 / 1p58 / 1p51 / 1p51 / 1p58 / 1p5
Ice Lake7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p151 / 1p58 / 1p5
Alder Lake8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p15
Sapphire Rapids8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p151 / 1p59 / 1p5
Lunar Lake7 / 2V2 V31 / 0.5V2 V38 / 2.33V2 V31 / 0.5V2 V3
Piledriver7 / 1.5FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 1FPU1 FPU21 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 48 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP21 / 1FP1 FP28 / 1FP1 FP2
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Shuffle by immediate: two bits of imm8 per result doubleword pick one of the four doublewords of the source.
VPSHUFD with imm8 = 0x61With imm8 = 0x61, result doublewords 3 to 0: a1, unchanged (bit 2 of k1 is 0), a0, a1.0123xmm2or m128a1110k1a1a0a1xmm101001001imm80x61

Example: imm8 = 0x61 (0110 0001 in binary). The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one doubleword from memory stands for every element of xmm2.

With imm8 = 0x61, result doublewords 3 to 0: a1, unchanged (bit 2 of k1 is 0), a0, a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    k = imm8 >> 2 * (i % 4) & 3
    j = i - i % 4 + k
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = src2.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPSHUFD xmm, xmm/m128, imm8 VPSHUFD ymm, ymm/m256, imm8
xmm, ymmexplicitwrite
xmm/m128, ymm/m256explicitread
imm8explicitread
VPSHUFD xmm {k}{z}, xmm/m128/m32bcst, imm8 VPSHUFD ymm {k}{z}, ymm/m256/m32bcst, imm8 VPSHUFD zmm {k}{z}, zmm/m512/m32bcst, imm8
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHUFD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_shuffle_epi32 __m128i _mm_shuffle_epi32(__m128i a, const int imm)

VPSHUFD xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_mask_shuffle_epi32 __m128i _mm_mask_shuffle_epi32(__m128i W, __mmask8 U, __m128i A, const int I)

VPSHUFD xmm {k}, xmm, imm8 EVEX.128 -mavx512vl

_mm_maskz_shuffle_epi32 __m128i _mm_maskz_shuffle_epi32(__mmask8 U, __m128i A, const int I)

VPSHUFD xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vl

_mm256_shuffle_epi32 __m256i _mm256_shuffle_epi32(__m256i a, const int imm)

VPSHUFD ymm, ymm, imm8 VEX.256 -mavx2

Clang's comment names VPSHUFB, the byte shuffle; this intrinsic shuffles doublewords by an immediate, and Clang emits VPSHUFD.

_mm256_mask_shuffle_epi32 __m256i _mm256_mask_shuffle_epi32(__m256i W, __mmask8 U, __m256i A, const int I)

VPSHUFD ymm {k}, ymm, imm8 EVEX.256 -mavx512vl

_mm256_maskz_shuffle_epi32 __m256i _mm256_maskz_shuffle_epi32(__mmask8 U, __m256i A, const int I)

VPSHUFD ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512vl

_mm512_shuffle_epi32 __m512i _mm512_shuffle_epi32(__m512i A, const int I)

VPSHUFD zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_shuffle_epi32 __m512i _mm512_mask_shuffle_epi32(__m512i W, __mmask16 U, __m512i A, const int I)

VPSHUFD zmm {k}, zmm, imm8 EVEX.512 -mavx512f

_mm512_maskz_shuffle_epi32 __m512i _mm512_maskz_shuffle_epi32(__mmask16 U, __m512i A, const int I)

VPSHUFD zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-426 (PSHUFD)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.