x86-64.net

Instruction

VPSHUFD

Rearranges doublewords within each 128-bit lane as an immediate selects.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPSHUFD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSHUFD xmm, m128, imm8 VPSHUFD_XMMdq_MEMdq_IMMbVEX.128.66.0F.WIG 70 /r ibAVX
VPSHUFD xmm, xmm, imm8 VPSHUFD_XMMdq_XMMdq_IMMbVEX.128.66.0F.WIG 70 /r ibAVX
VPSHUFD ymm, m256, imm8 VPSHUFD_YMMqq_MEMqq_IMMbVEX.256.66.0F.WIG 70 /r ibAVX2
VPSHUFD ymm, ymm, imm8 VPSHUFD_YMMqq_YMMqq_IMMbVEX.256.66.0F.WIG 70 /r ibAVX2
VPSHUFD zmm {k}{z}, zmm, imm8 VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512EVEX.512.66.0F.W0 70 /r ibAVX10.1 or AVX512F
VPSHUFD zmm {k}{z}, m512/m32bcst, imm8 VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.512.66.0F.W0 70 /r ibAVX10.1 or AVX512F
VPSHUFD xmm {k}{z}, xmm, imm8 VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512EVEX.128.66.0F.W0 70 /r ibAVX10.1 or AVX512F + AVX512VL
VPSHUFD xmm {k}{z}, m128/m32bcst, imm8 VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.128.66.0F.W0 70 /r ibAVX10.1 or AVX512F + AVX512VL
VPSHUFD ymm {k}{z}, ymm, imm8 VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512EVEX.256.66.0F.W0 70 /r ibAVX10.1 or AVX512F + AVX512VL
VPSHUFD ymm {k}{z}, m256/m32bcst, imm8 VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.256.66.0F.W0 70 /r ibAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHUFD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_shuffle_epi32 __m128i _mm_shuffle_epi32(__m128i a, const int imm)

VPSHUFD xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_mask_shuffle_epi32 __m128i _mm_mask_shuffle_epi32(__m128i W, __mmask8 U, __m128i A, const int I)

VPSHUFD xmm {k}, xmm, imm8 EVEX.128 -mavx512vl

_mm_maskz_shuffle_epi32 __m128i _mm_maskz_shuffle_epi32(__mmask8 U, __m128i A, const int I)

VPSHUFD xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vl

_mm256_shuffle_epi32 __m256i _mm256_shuffle_epi32(__m256i a, const int imm)

VPSHUFD ymm, ymm, imm8 VEX.256 -mavx2

Clang's comment names VPSHUFB, the byte shuffle; this intrinsic shuffles doublewords by an immediate, and Clang emits VPSHUFD.

_mm256_mask_shuffle_epi32 __m256i _mm256_mask_shuffle_epi32(__m256i W, __mmask8 U, __m256i A, const int I)

VPSHUFD ymm {k}, ymm, imm8 EVEX.256 -mavx512vl

_mm256_maskz_shuffle_epi32 __m256i _mm256_maskz_shuffle_epi32(__mmask8 U, __m256i A, const int I)

VPSHUFD ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512vl

_mm512_shuffle_epi32 __m512i _mm512_shuffle_epi32(__m512i A, const int I)

VPSHUFD zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_shuffle_epi32 __m512i _mm512_mask_shuffle_epi32(__m512i W, __mmask16 U, __m512i A, const int I)

VPSHUFD zmm {k}, zmm, imm8 EVEX.512 -mavx512f

_mm512_maskz_shuffle_epi32 __m512i _mm512_maskz_shuffle_epi32(__mmask16 U, __m512i A, const int I)

VPSHUFD zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.