x86-64.net

Instruction

VPSHUFLW

Rearranges the lower four words of each 128-bit lane as an immediate selects.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPSHUFLW rearranges the four words in the low quadword of each 128-bit lane as an immediate says and copies the high quadword through: the VEX and EVEX form of SSE2’s PSHUFLW, whose page explains the immediate and the word shuffles of SSE2. VPSHUFHW is its mirror image and shows where compilers prefer other instructions. The ymm and zmm forms apply one immediate to every lane, memory needs no alignment, and the destination is zeroed above the vector length. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX512BW (with AVX512VL below 512 bits) or AVX10.1 and add a write mask per word, but no broadcast. On Zen 5:

  • vpshuflw ymm8, ymmword ptr [mem], 0xd3 put word 3 of each lane in words 0 and 3 and words 0 and 1 in words 1 and 2, lane by lane, and copied the high quadwords.
  • vpshuflw xmm9{k1}{z}, xmmword ptr [mem], 0x16, with A0h in the low byte of K1, kept only words 5 and 7, two of the copied ones, and zeroed all four shuffled words.

Narrowing in our builds

For the SSE2 baseline, Clang 23 at -O2 narrows int32_t elements to int16_t with PSHUFLW and PSHUFHW E8h, which pair up the low words of each quadword’s doublewords, and a PSHUFD E8h that joins the pairs. The VEX forms take no part in it. In our builds over fixed-size arrays, a[i] = (int16_t)w[i] becomes, with -march=x86-64-v3, a VPSHUFB and a VPERMQ per vector in Clang and a VPACKUSDW of the masked words in GCC 14; with -v4, Clang stores each vector through VPMOVDW and GCC combines two with VPERMT2W.

VPSHUFLW appears when the shuffle itself stays in the low quadwords: reversing words 0 to 3 of each lane is one vpshuflw ymm0, ymm0, 0x1b in both compilers at -v3 and -v4.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 1 cycle, four per cycle on pipes FP0 to FP3, as for VPSHUFHW.

Forms

Every encoding of VPSHUFLW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSHUFLW xmm, m128, imm8 VPSHUFLW_XMMdq_MEMdq_IMMbVEX.128.F2.0F.WIG 70 /r ibAVX
VPSHUFLW xmm, xmm, imm8 VPSHUFLW_XMMdq_XMMdq_IMMbVEX.128.F2.0F.WIG 70 /r ibAVX
VPSHUFLW ymm, m256, imm8 VPSHUFLW_YMMqq_MEMqq_IMMbVEX.256.F2.0F.WIG 70 /r ibAVX2
VPSHUFLW ymm, ymm, imm8 VPSHUFLW_YMMqq_YMMqq_IMMbVEX.256.F2.0F.WIG 70 /r ibAVX2
VPSHUFLW xmm {k}{z}, xmm, imm8 VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512EVEX.128.F2.0F.WIG 70 /r ibAVX10.1 or AVX512BW + AVX512VL
VPSHUFLW xmm {k}{z}, m128, imm8 VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512EVEX.128.F2.0F.WIG 70 /r ibAVX10.1 or AVX512BW + AVX512VL
VPSHUFLW ymm {k}{z}, ymm, imm8 VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512EVEX.256.F2.0F.WIG 70 /r ibAVX10.1 or AVX512BW + AVX512VL
VPSHUFLW ymm {k}{z}, m256, imm8 VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512EVEX.256.F2.0F.WIG 70 /r ibAVX10.1 or AVX512BW + AVX512VL
VPSHUFLW zmm {k}{z}, zmm, imm8 VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512EVEX.512.F2.0F.WIG 70 /r ibAVX10.1 or AVX512BW
VPSHUFLW zmm {k}{z}, m512, imm8 VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512EVEX.512.F2.0F.WIG 70 /r ibAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, m128, imm8
xmm {k}{z}, m128, imm8no mask		xmm, xmm, imm8
xmm {k}{z}, xmm, imm8no mask
ymm {k}{z}, ymm, imm8no mask		ymm, m256, imm8
ymm {k}{z}, m256, imm8no mask		ymm, ymm, imm8xmm {k}{z}, xmm, imm8with a mask, zeroing
ymm {k}{z}, ymm, imm8with a mask, zeroing		xmm {k}{z}, m128, imm8with a mask, zeroingymm {k}{z}, m256, imm8with a mask, zeroingzmm {k}{z}, zmm, imm8no maskzmm {k}{z}, zmm, imm8with a mask, zeroingzmm {k}{z}, m512, imm8no maskzmm {k}{z}, m512, imm8with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell, Skylake7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake-SP7 / 1p51 / 1p58 / 1p51 / 1p51 / 1p57 / 1p58 / 1p51 / 1p51 / 1p58 / 1p58 / 1p5
Ice Lake7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p151 / 0.5p157 / 0.5p158 / 0.5p151 / 1p51 / 1p58 / 1p58 / 1p5
Alder Lake8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p15
Sapphire Rapids8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p153 / 0.5p1511 / 0.5p1511 / 0.5p151 / 1p53 / 1p59 / 1p511 / 1p5
Lunar Lake7 / 2V2 V31 / 0.5V2 V38 / 2.33V2 V31 / 0.5V2 V3
Piledriver7 / 1.5FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 1FPU1 FPU21 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 48 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP28 / 0.5FP1 FP21 / 1FP1 FP21 / 1FP1 FP28 / 1FP1 FP28 / 1FP1 FP2
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Shuffle by immediate: two bits of imm8 per word pick each of the low four words from the low four; the high four are copied.
VPSHUFLW with imm8 = 0x1BWith imm8 = 0x1B, result words 7 to 0: a7, unchanged (bit 6 of k1 is 0), a5, a4, a0, a1, a2, a3.01234567xmm2or m128a11111110k1a3a2a1a0a4a5a7xmm111100100imm80x1B

Example: imm8 = 0x1B (0001 1011 in binary). The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

With imm8 = 0x1B, result words 7 to 0: a7, unchanged (bit 6 of k1 is 0), a5, a4, a0, a1, a2, a3.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    k = imm8 >> 2 * (i % 4) & 3
    j = i - i % 4 + k if i % 8 < 4 else i  # the high four copied
    if k1[i]:                              # 1 without a write mask
        zmm1.w[i] = src2.w[j]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPSHUFLW xmm, xmm/m128, imm8 VPSHUFLW ymm, ymm/m256, imm8
xmm, ymmexplicitwrite
xmm/m128, ymm/m256explicitread
imm8explicitread
VPSHUFLW xmm {k}{z}, xmm/m128, imm8 VPSHUFLW ymm {k}{z}, ymm/m256, imm8 VPSHUFLW zmm {k}{z}, zmm/m512, imm8
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m128, ymm/m256, zmm/m512explicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSHUFLW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_shufflelo_epi16 __m128i _mm_shufflelo_epi16(__m128i a, const int imm)

VPSHUFLW xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_mask_shufflelo_epi16 __m128i _mm_mask_shufflelo_epi16(__m128i W, __mmask8 U, __m128i A, const int imm)

VPSHUFLW xmm {k}, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_shufflelo_epi16 __m128i _mm_maskz_shufflelo_epi16(__mmask8 U, __m128i A, const int imm)

VPSHUFLW xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm256_shufflelo_epi16 __m256i _mm256_shufflelo_epi16(__m256i a, const int imm)

VPSHUFLW ymm, ymm, imm8 VEX.256 -mavx2

_mm256_mask_shufflelo_epi16 __m256i _mm256_mask_shufflelo_epi16(__m256i W, __mmask16 U, __m256i A, const int imm)

VPSHUFLW ymm {k}, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_shufflelo_epi16 __m256i _mm256_maskz_shufflelo_epi16(__mmask16 U, __m256i A, const int imm)

VPSHUFLW ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm512_shufflelo_epi16 __m512i _mm512_shufflelo_epi16(__m512i A, const int imm)

VPSHUFLW zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_mask_shufflelo_epi16 __m512i _mm512_mask_shufflelo_epi16(__m512i W, __mmask32 U, __m512i A, const int imm)

VPSHUFLW zmm {k}, zmm, imm8 EVEX.512 -mavx512bw

_mm512_maskz_shufflelo_epi16 __m512i _mm512_maskz_shufflelo_epi16(__mmask32 U, __m512i A, const int imm)

VPSHUFLW zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-433 (PSHUFLW)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.