VPSIGND instruction (AVX, AVX2)

VPSIGND applies the sign of each doubleword of its second source to the matching doubleword of the first, negating, clearing or keeping it: the VEX form of PSIGND, whose page covers the operation. Like VPSIGNW it adds a separate destination, memory at any alignment and, with AVX2, the 256-bit form, and has no EVEX encoding, so no masking, no broadcast, no ZMM form and no access to registers 16 to 31. The negation wraps: on Zen 5, the recorded vpsignd xmm1, xmm2, xmm3 turned 7FFFFFFFh into 80000001h and left 80000000h as 80000000h under negative doublewords; vpsignd ymm12, ymm6, ymm6, one register signed by itself, also kept 80000000h, the edge VPABSD has too.

In compiled code

In our builds at -O2 with -march=x86-64-v3, GCC 14 and Clang 23 keep _mm256_sign_epi32 as VPSIGND, _mm256_sign_epi32(a, a) included, but derive it from none of these loops over int32_t arrays:

The three-way rule. c[i] < 0 ? -b[i] : (c[i] == 0 ? 0 : b[i]) is VPCMPEQD against zero and VPANDN to clear, VPSUBD to negate and VBLENDVPS to pick the negation. The blend chooses by the top bit of each element of c itself, so no compare is needed for the sign, unlike for words, where VPBLENDVB reads the sign of each byte and VPCMPGTW must spread it.
Copying a sign. c[i] < 0 ? -abs(b[i]) : abs(b[i]) takes VPABSD, a VPCMPGTD and then a select in GCC or an XOR and a subtraction in Clang.

With -march=x86-64-v4 both compilers do the three-way rule with masks: a zero-masked move where c is not zero, then a VPSUBD from zero merge-masked where it is negative, which in AVX-512 code replaces the missing EVEX form. AMD’s latency spreadsheet for Zen 5 gives VPSIGND a latency of two cycles and two per cycle on pipes FP0 and FP3.

Forms

Every encoding of VPSIGND that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPSIGND xmm, xmm, m128` VPSIGND_XMMdq_XMMdq_MEMdq	`VEX.128.66.0F38.WIG 0A /r`	AVX
`VPSIGND xmm, xmm, xmm` VPSIGND_XMMdq_XMMdq_XMMdq	`VEX.128.66.0F38.WIG 0A /r`	AVX
`VPSIGND ymm, ymm, m256` VPSIGND_YMMqq_YMMqq_MEMqq	`VEX.256.66.0F38.WIG 0A /r`	AVX2
`VPSIGND ymm, ymm, ymm` VPSIGND_YMMqq_YMMqq_YMMqq	`VEX.256.66.0F38.WIG 0A /r`	AVX2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Every doubleword works alike: 4 and 8 doublewords in the xmm and ymm forms.

Result doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    a = ymm2.d[i]
    b = src3.d[i]
    sb = src3.sd[i]
    if sb < 0:
        ymm1.d[i] = -a
    elif b == 0:
        ymm1.d[i] = 0
    else:
        ymm1.d[i] = a
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPSIGND xmm, xmm, xmm/m128` `VPSIGND ymm, ymm, ymm/m256`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSIGND, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sign_epi32` `__m128i _mm_sign_epi32(__m128i __a, __m128i __b)`	`VPSIGND xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm256_sign_epi32` `__m256i _mm256_sign_epi32(__m256i __a, __m256i __b)`	`VPSIGND ymm, ymm, ymm` VEX.256 -mavx2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

In compiled code#