VPSIGNW instruction (AVX, AVX2)

VPSIGNW negates, clears or keeps each word of its first source as the matching word of the second is negative, zero or positive: the VEX form of PSIGNW, whose page, with PSIGNB’s, covers the rule. It adds a separate destination and memory at any alignment; VEX.128 needs AVX and VEX.256 AVX2. There is no EVEX encoding: it reaches only XMM0 to XMM15 and YMM0 to YMM15, with no masking and no 512-bit width. The negation wraps. On Zen 5, the recorded vpsignw ymm7, ymm11, ymmword ptr [mem] turned FFFFh into 0001h and 7FFFh into 8001h under negative words, left 8000h as it was, and cleared 0001h under a zero word in the upper lane.

In compiled code

In our builds at -O2, GCC 14 and Clang 23 emit VPSIGNW only for _mm_sign_epi16 and _mm256_sign_epi16, also with -march=x86-64-v4, where it stays a VEX instruction. Signing by -1 is not turned into a negation: _mm256_sign_epi16(a, _mm256_set1_epi16(-1)) is VPCMPEQD and VPSIGNW.

The same rule in C over int16_t arrays, c[i] < 0 ? -b[i] : (c[i] == 0 ? 0 : b[i]), never becomes VPSIGNW. With -march=x86-64-v3 both compilers compare with VPCMPEQW and VPCMPGTW, clear with VPANDN, negate with VPSUBW and select with VPBLENDVB. With -v4 they use masks instead: a zero-masked move keeps the words whose sign source is not zero, and a VPSUBW from zero, merge-masked by the negative ones, negates in place. That pair is how AVX-512 code does the work of the missing EVEX form.

AMD’s latency spreadsheet for Zen 5 gives VPSIGNW a latency of two cycles and two per cycle on pipes FP0 and FP3, as for the legacy form.

Forms

Every encoding of VPSIGNW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPSIGNW xmm, xmm, m128` VPSIGNW_XMMdq_XMMdq_MEMdq	`VEX.128.66.0F38.WIG 09 /r`	AVX
`VPSIGNW xmm, xmm, xmm` VPSIGNW_XMMdq_XMMdq_XMMdq	`VEX.128.66.0F38.WIG 09 /r`	AVX
`VPSIGNW ymm, ymm, m256` VPSIGNW_YMMqq_YMMqq_MEMqq	`VEX.256.66.0F38.WIG 09 /r`	AVX2
`VPSIGNW ymm, ymm, ymm` VPSIGNW_YMMqq_YMMqq_YMMqq	`VEX.256.66.0F38.WIG 09 /r`	AVX2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 8 and 16 words in the xmm and ymm forms.

Result word i comes from word i of xmm2 and xmm3. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    a = ymm2.w[i]
    b = src3.w[i]
    sb = src3.sw[i]
    if sb < 0:
        ymm1.w[i] = -a
    elif b == 0:
        ymm1.w[i] = 0
    else:
        ymm1.w[i] = a
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPSIGNW xmm, xmm, xmm/m128` `VPSIGNW ymm, ymm, ymm/m256`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSIGNW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sign_epi16` `__m128i _mm_sign_epi16(__m128i __a, __m128i __b)`	`VPSIGNW xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm256_sign_epi16` `__m256i _mm256_sign_epi16(__m256i __a, __m256i __b)`	`VPSIGNW ymm, ymm, ymm` VEX.256 -mavx2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

In compiled code#